mirror of https://github.com/m-labs/artiq.git
drtio: share CDC
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parent
078c862618
commit
88b7529d09
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@ -3,63 +3,12 @@
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.cdc import PulseSynchronizer
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from artiq.gateware.rtio.cdc import GrayCodeTransfer, BlindTransfer
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from artiq.gateware.drtio.cdc import CrossDomainRequest, CrossDomainNotification
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from artiq.gateware.drtio.rt_serializer import *
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class _CrossDomainRequest(Module):
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def __init__(self, domain,
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req_stb, req_ack, req_data,
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srv_stb, srv_ack, srv_data):
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dsync = getattr(self.sync, domain)
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request = PulseSynchronizer("sys", domain)
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reply = PulseSynchronizer(domain, "sys")
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self.submodules += request, reply
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ongoing = Signal()
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self.comb += request.i.eq(~ongoing & req_stb)
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self.sync += [
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req_ack.eq(reply.o),
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If(req_stb, ongoing.eq(1)),
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If(req_ack, ongoing.eq(0))
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]
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if req_data is not None:
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req_data_r = Signal.like(req_data)
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req_data_r.attr.add("no_retiming")
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self.sync += If(req_stb, req_data_r.eq(req_data))
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dsync += [
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If(request.o, srv_stb.eq(1)),
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If(srv_ack, srv_stb.eq(0))
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]
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if req_data is not None:
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dsync += If(request.o, srv_data.eq(req_data_r))
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self.comb += reply.i.eq(srv_stb & srv_ack)
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class _CrossDomainNotification(Module):
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def __init__(self, domain,
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emi_stb, emi_data,
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rec_stb, rec_ack, rec_data):
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emi_data_r = Signal(len(emi_data))
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emi_data_r.attr.add("no_retiming")
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dsync = getattr(self.sync, domain)
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dsync += If(emi_stb, emi_data_r.eq(emi_data))
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ps = PulseSynchronizer(domain, "sys")
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self.submodules += ps
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self.comb += ps.i.eq(emi_stb)
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self.sync += [
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If(rec_ack, rec_stb.eq(0)),
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If(ps.o,
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rec_data.eq(emi_data_r),
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rec_stb.eq(1)
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)
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]
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class RTPacketMaster(Module):
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def __init__(self, link_layer, sr_fifo_depth=4):
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# all interface signals in sys domain unless otherwise specified
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@ -206,19 +155,19 @@ class RTPacketMaster(Module):
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# CDC
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buffer_space_not = Signal()
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buffer_space = Signal(16)
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self.submodules += _CrossDomainNotification("rtio_rx",
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self.submodules += CrossDomainNotification("rtio_rx", "sys",
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buffer_space_not, buffer_space,
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self.buffer_space_not, self.buffer_space_not_ack, self.buffer_space)
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set_time_stb = Signal()
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set_time_ack = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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self.submodules += CrossDomainRequest("rtio",
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self.set_time_stb, self.set_time_ack, None,
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set_time_stb, set_time_ack, None)
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echo_stb = Signal()
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echo_ack = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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self.submodules += CrossDomainRequest("rtio",
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self.echo_stb, self.echo_ack, None,
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echo_stb, echo_ack, None)
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@ -227,7 +176,7 @@ class RTPacketMaster(Module):
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read_is_overflow = Signal()
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read_data = Signal(32)
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read_timestamp = Signal(64)
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self.submodules += _CrossDomainNotification("rtio_rx",
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self.submodules += CrossDomainNotification("rtio_rx", "sys",
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read_not,
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Cat(read_no_event, read_is_overflow, read_data, read_timestamp),
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@ -3,8 +3,8 @@ import random
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from migen import *
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from artiq.gateware.drtio.rt_packet_master import (_CrossDomainRequest,
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_CrossDomainNotification)
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from artiq.gateware.drtio.cdc import CrossDomainRequest, CrossDomainNotification
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class TestCDC(unittest.TestCase):
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def test_cross_domain_request(self):
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@ -43,7 +43,7 @@ class TestCDC(unittest.TestCase):
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yield srv_ack.eq(0)
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yield
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dut = _CrossDomainRequest("srv",
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dut = CrossDomainRequest("srv",
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req_stb, req_ack, req_data,
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srv_stb, srv_ack, srv_data)
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run_simulation(dut,
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@ -85,7 +85,7 @@ class TestCDC(unittest.TestCase):
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for j in range(prng.randrange(0, 3)):
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yield
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dut = _CrossDomainNotification("emi",
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dut = CrossDomainNotification("emi", "sys",
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emi_stb, emi_data,
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rec_stb, rec_ack, rec_data)
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run_simulation(dut,
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