mirror of https://github.com/m-labs/artiq.git
sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad
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@ -400,6 +400,17 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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self.csr_devices.append("sysref_sampler")
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
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# timing analysis. Disable the latter for IOBUFDS.
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# See:
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# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
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# FIXME: this is a bit zealous. Xilinx SR in progress to find a more selective command.
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platform.add_platform_command(
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"set_false_path -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
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class Master(MiniSoC, AMPSoC):
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"""
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DRTIO master with 2 SFP ports plus 8 lanes on RTM.
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@ -528,6 +539,7 @@ class Master(MiniSoC, AMPSoC):
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iostandard="LVDS")
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eem.Zotino.add_std(self, 3, ttl_simple.Output,
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iostandard="LVDS")
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workaround_us_lvds_tristate(platform)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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