rtlink: sanity-check parameters

artiq/gateware/rtio/rtlink.py

@@ -8,6 +8,10 @@ class OInterface:
         self.stb = Signal()
         self.busy = Signal()
 
+        assert 0 <= data_width <= 512
+        assert 0 <= address_width <= 8
+        assert 0 <= fine_ts_width <= 4
+
         if data_width:
             self.data = Signal(data_width, reset_less=True)
         if address_width:
@@ -35,6 +39,9 @@ class IInterface:
                  timestamped=True, fine_ts_width=0, delay=0):
         self.stb = Signal()
 
+        assert 0 <= data_width <= 32
+        assert 0 <= fine_ts_width <= 4
+
         if data_width:
             self.data = Signal(data_width, reset_less=True)
         if fine_ts_width: