mirror of https://github.com/m-labs/artiq
Merge branch 'master' into new
commit
1b841805f6
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@ -26,22 +26,22 @@ _AD9910_REG_CFR1 = 0x00
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_AD9910_REG_CFR2 = 0x01
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_AD9910_REG_CFR3 = 0x02
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_AD9910_REG_AUX_DAC = 0x03
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_AD9910_REG_IO_UPD = 0x04
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_AD9910_REG_IO_UPDATE = 0x04
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_AD9910_REG_FTW = 0x07
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_AD9910_REG_POW = 0x08
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_AD9910_REG_ASF = 0x09
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_AD9910_REG_MSYNC = 0x0A
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_AD9910_REG_DRAMPL = 0x0B
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_AD9910_REG_DRAMPS = 0x0C
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_AD9910_REG_DRAMPR = 0x0D
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_AD9910_REG_PR0 = 0x0E
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_AD9910_REG_PR1 = 0x0F
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_AD9910_REG_PR2 = 0x10
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_AD9910_REG_PR3 = 0x11
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_AD9910_REG_PR4 = 0x12
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_AD9910_REG_PR5 = 0x13
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_AD9910_REG_PR6 = 0x14
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_AD9910_REG_PR7 = 0x15
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_AD9910_REG_SYNC = 0x0a
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_AD9910_REG_RAMP_LIMIT = 0x0b
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_AD9910_REG_RAMP_STEP = 0x0c
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_AD9910_REG_RAMP_RATE = 0x0d
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_AD9910_REG_PROFILE0 = 0x0e
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_AD9910_REG_PROFILE1 = 0x0f
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_AD9910_REG_PROFILE2 = 0x10
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_AD9910_REG_PROFILE3 = 0x11
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_AD9910_REG_PROFILE4 = 0x12
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_AD9910_REG_PROFILE5 = 0x13
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_AD9910_REG_PROFILE6 = 0x14
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_AD9910_REG_PROFILE7 = 0x15
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_AD9910_REG_RAM = 0x16
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@ -256,7 +256,7 @@ class AD9910:
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@kernel
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def set_mu(self, ftw, pow=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT,
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ref_time=-1):
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ref_time=-1, profile=0):
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"""Set profile 0 data in machine units.
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This uses machine units (FTW, POW, ASF). The frequency tuning word
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@ -276,6 +276,7 @@ class AD9910:
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by :meth:`set_phase_mode` for this call.
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:param ref_time: Fiducial time used to compute absolute or tracking
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phase updates. In machine units as obtained by `now_mu()`.
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:param profile: Profile number to set (0-7, default: 0).
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:return: Resulting phase offset word after application of phase
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tracking offset. When using :const:`PHASE_MODE_CONTINUOUS` in
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subsequent calls, use this value as the "current" phase.
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@ -297,7 +298,7 @@ class AD9910:
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# is equivalent to an output pipeline latency.
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dt = int32(now_mu()) - int32(ref_time)
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pow += dt*ftw*self.sysclk_per_mu >> 16
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self.write64(_AD9910_REG_PR0, (asf << 16) | pow, ftw)
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self.write64(_AD9910_REG_PROFILE0 + profile, (asf << 16) | pow, ftw)
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delay_mu(int64(self.io_update_delay))
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self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYSCLK
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at_mu(now_mu() & ~0xf)
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@ -332,7 +333,7 @@ class AD9910:
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@kernel
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def set(self, frequency, phase=0.0, amplitude=1.0,
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phase_mode=_PHASE_MODE_DEFAULT, ref_time=-1):
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phase_mode=_PHASE_MODE_DEFAULT, ref_time=-1, profile=0):
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"""Set profile 0 data in SI units.
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.. seealso:: :meth:`set_mu`
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@ -342,11 +343,12 @@ class AD9910:
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:param asf: Amplitude in units of full scale
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:param phase_mode: Phase mode constant
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:param ref_time: Fiducial time stamp in machine units
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:param profile: Profile to affect
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:return: Resulting phase offset in turns
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"""
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return self.pow_to_turns(self.set_mu(
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self.frequency_to_ftw(frequency), self.turns_to_pow(phase),
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self.amplitude_to_asf(amplitude), phase_mode, ref_time))
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self.amplitude_to_asf(amplitude), phase_mode, ref_time, profile))
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@kernel
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def set_att_mu(self, att):
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@ -389,7 +391,7 @@ class AD9910:
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:param window: Symmetric SYNC_IN validation window (0-15) in
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steps of ~75ps for both hold and setup margin.
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"""
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self.write32(_AD9910_REG_MSYNC,
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self.write32(_AD9910_REG_SYNC,
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(window << 28) | # SYNC S/H validation delay
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(1 << 27) | # SYNC receiver enable
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(0 << 26) | # SYNC generator disable
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@ -466,17 +468,18 @@ class AD9910:
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raise ValueError("no valid window/delay")
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@kernel
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def measure_io_update_alignment(self, io_up_delay):
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def measure_io_update_alignment(self, delay_start, delay_stop):
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"""Use the digital ramp generator to locate the alignment between
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IO_UPDATE and SYNC_CLK.
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The ramp generator is set up to a linear frequency ramp
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(dFTW/t_SYNC_CLK=1) and started at a RTIO time stamp.
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(dFTW/t_SYNC_CLK=1) and started at a coarse RTIO time stamp plus
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`delay_start` and stopped at a coarse RTIO time stamp plus
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`delay_stop`.
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After scanning the alignment, an IO_UPDATE delay midway between two
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edges should be chosen.
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:return: odd/even SYNC_CLK cycle indicator
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:param delay_start: Start IO_UPDATE delay in machine units.
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:param delay_stop: Stop IO_UPDATE delay in machine units.
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:return: Odd/even SYNC_CLK cycle indicator.
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"""
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# set up DRG
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# DRG ACC autoclear and LRR on io update
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@ -484,19 +487,21 @@ class AD9910:
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# DRG -> FTW, DRG enable
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self.write32(_AD9910_REG_CFR2, 0x01090000)
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# no limits
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self.write64(_AD9910_REG_DRAMPL, -1, 0)
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self.write64(_AD9910_REG_RAMP_LIMIT, -1, 0)
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# DRCTL=0, dt=1 t_SYNC_CLK
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self.write32(_AD9910_REG_DRAMPR, 0x00010000)
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self.write32(_AD9910_REG_RAMP_RATE, 0x00010000)
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# dFTW = 1, (work around negative slope)
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self.write64(_AD9910_REG_DRAMPS, -1, 0)
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at_mu(now_mu() + 0x10 & ~0xf) # align to RTIO/2
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self.cpld.io_update.pulse_mu(8)
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self.write64(_AD9910_REG_RAMP_STEP, -1, 0)
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# delay io_update after RTIO/2 edge
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t = now_mu() + 0x10 & ~0xf
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at_mu(t + delay_start)
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self.cpld.io_update.pulse_mu(32 - delay_start) # realign
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# disable DRG autoclear and LRR on io_update
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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# stop DRG
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self.write64(_AD9910_REG_DRAMPS, 0, 0)
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at_mu((now_mu() + 0x10 & ~0xf) + io_up_delay) # delay
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self.cpld.io_update.pulse_mu(32 - io_up_delay) # realign
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self.write64(_AD9910_REG_RAMP_STEP, 0, 0)
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at_mu(t + 0x1000 + delay_stop)
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self.cpld.io_update.pulse_mu(32 - delay_stop) # realign
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ftw = self.read32(_AD9910_REG_FTW) # read out effective FTW
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delay(100*us) # slack
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# disable DRG
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@ -510,22 +515,35 @@ class AD9910:
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Scan through increasing IO_UPDATE delays until a delay is found that
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lets IO_UPDATE be registered in the next SYNC_CLK cycle. Return a
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IO_UPDATE delay that is midway between two such SYNC_CLK transitions.
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IO_UPDATE delay that is as far away from that SYNC_CLK edge
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as possible.
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This method assumes that the IO_UPDATE TTLOut device has one machine
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unit resolution (SERDES) and that the ratio between fine RTIO frequency
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(RTIO time machine units) and SYNC_CLK is 4.
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unit resolution (SERDES).
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:return: Stable IO_UPDATE delay to be passed to the constructor
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:class:`AD9910` via the device database.
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"""
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period = 4 # f_RTIO/f_SYNC = 4
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max_delay = 8 # mu, 1 ns
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d0 = self.io_update_delay
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t0 = int32(self.measure_io_update_alignment(d0))
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for i in range(max_delay - 1):
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t = self.measure_io_update_alignment(
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(d0 + i + 1) & (max_delay - 1))
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if t != t0:
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return (d0 + i + period//2) & (period - 1)
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period = self.sysclk_per_mu * 4 # SYNC_CLK period
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repeat = 100
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for i in range(period):
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t = 0
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# check whether the sync edge is strictly between i, i+2
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for j in range(repeat):
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t += self.measure_io_update_alignment(i, i + 2)
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if t != 0: # no certain edge
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continue
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# check left/right half: i,i+1 and i+1,i+2
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t1 = [0, 0]
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for j in range(repeat):
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t1[0] += self.measure_io_update_alignment(i, i + 1)
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t1[1] += self.measure_io_update_alignment(i + 1, i + 2)
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if ((t1[0] == 0 and t1[1] == 0) or
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(t1[0] == repeat and t1[1] == repeat)):
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# edge is not close to i + 1, can't interpret result
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raise ValueError(
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"no clear IO_UPDATE-SYNC_CLK alignment edge found")
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else:
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# the good delay is period//2 after the edge
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return (i + 1 + period//2) & (period - 1)
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raise ValueError("no IO_UPDATE-SYNC_CLK alignment edge found")
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@ -14,7 +14,8 @@ SPI_CONFIG = (0*spi.SPI_OFFLINE | 0*spi.SPI_END |
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# SPI clock write and read dividers
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SPIT_CFG_WR = 2
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SPIT_CFG_RD = 16
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SPIT_ATT_WR = 2
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# 30 MHz fmax, 20 ns setup, 40 ns shift to latch (limiting)
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SPIT_ATT_WR = 6
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SPIT_ATT_RD = 16
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SPIT_DDS_WR = 2
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SPIT_DDS_RD = 16
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@ -174,7 +175,7 @@ class CPLD:
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self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0,
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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sync_sel=sync_sel, rst=0, io_rst=0)
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self.att_reg = att
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self.att_reg = int32(att)
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self.sync_div = sync_div
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@kernel
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@ -299,7 +300,8 @@ class CPLD:
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:param channel: Attenuator channel (0-3).
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:param att: Attenuation setting in dB. Higher value is more
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attenuation.
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attenuation. Minimum attenuation is 0*dB, maximum attenuation is
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31.5*dB.
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"""
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self.set_att_mu(channel, 255 - int32(round(att*8)))
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@ -333,3 +335,15 @@ class CPLD:
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ftw = ftw_max//div
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assert ftw*div == ftw_max
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self.sync.set_mu(ftw)
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@kernel
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def set_profile(self, profile):
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"""Set the PROFILE pins.
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The PROFILE pins are common to all four DDS channels.
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:param profile: PROFILE pins in numeric representation (0-7).
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"""
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cfg = self.cfg_reg & ~(7 << CFG_PROFILE)
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cfg |= (profile & 7) << CFG_PROFILE
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self.cfg_write(cfg)
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@ -242,6 +242,12 @@ mod ddr {
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ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1));
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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}
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}
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for _ in 0..DDRPHY_MAX_DELAY {
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let mut working = true;
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@ -327,6 +333,12 @@ mod ddr {
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let mut max_seen_valid = 0;
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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}
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}
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for delay in 0..DDRPHY_MAX_DELAY {
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let mut valid = true;
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@ -384,6 +396,12 @@ mod ddr {
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// Set delay to the middle
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ddrphy::rdly_dq_rst_write(1);
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#[cfg(soc_platform = "kasli")]
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{
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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}
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}
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for _ in 0..mean_delay {
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ddrphy::rdly_dq_inc_write(1);
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}
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@ -541,7 +541,7 @@ class SUServo(_EEM):
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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|
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pads = target.platform.request("{}_dds_reset".format(eem_urukul1))
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pads = target.platform.request("{}_dds_reset_sync_in".format(eem_urukul1))
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target.specials += DifferentialOutput(0, pads.p, pads.n)
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for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
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|
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@ -275,6 +275,78 @@ class _RangeScan(LayoutWidget):
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randomize.setChecked(state["randomize"])
|
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|
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|
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class _CenterScan(LayoutWidget):
|
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def __init__(self, procdesc, state):
|
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LayoutWidget.__init__(self)
|
||||
|
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scale = procdesc["scale"]
|
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|
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def apply_properties(widget):
|
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widget.setDecimals(procdesc["ndecimals"])
|
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if procdesc["global_min"] is not None:
|
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widget.setMinimum(procdesc["global_min"]/scale)
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else:
|
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widget.setMinimum(float("-inf"))
|
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if procdesc["global_max"] is not None:
|
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widget.setMaximum(procdesc["global_max"]/scale)
|
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else:
|
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widget.setMaximum(float("inf"))
|
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if procdesc["global_step"] is not None:
|
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widget.setSingleStep(procdesc["global_step"]/scale)
|
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if procdesc["unit"]:
|
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widget.setSuffix(" " + procdesc["unit"])
|
||||
|
||||
center = ScientificSpinBox()
|
||||
disable_scroll_wheel(center)
|
||||
apply_properties(center)
|
||||
center.setPrecision()
|
||||
center.setRelativeStep()
|
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center.setValue(state["center"])
|
||||
self.addWidget(center, 0, 1)
|
||||
self.addWidget(QtWidgets.QLabel("Center:"), 0, 0)
|
||||
|
||||
span = ScientificSpinBox()
|
||||
disable_scroll_wheel(span)
|
||||
apply_properties(span)
|
||||
span.setPrecision()
|
||||
span.setRelativeStep()
|
||||
span.setMinimum(0)
|
||||
span.setValue(state["span"])
|
||||
self.addWidget(span, 1, 1)
|
||||
self.addWidget(QtWidgets.QLabel("Span:"), 1, 0)
|
||||
|
||||
step = ScientificSpinBox()
|
||||
disable_scroll_wheel(step)
|
||||
apply_properties(step)
|
||||
step.setPrecision()
|
||||
step.setRelativeStep()
|
||||
step.setMinimum(0)
|
||||
step.setValue(state["step"])
|
||||
self.addWidget(step, 2, 1)
|
||||
self.addWidget(QtWidgets.QLabel("Step:"), 2, 0)
|
||||
|
||||
randomize = QtWidgets.QCheckBox("Randomize")
|
||||
self.addWidget(randomize, 3, 1)
|
||||
randomize.setChecked(state["randomize"])
|
||||
|
||||
def update_center(value):
|
||||
state["center"] = value*scale
|
||||
|
||||
def update_span(value):
|
||||
state["span"] = value*scale
|
||||
|
||||
def update_step(value):
|
||||
state["step"] = value*scale
|
||||
|
||||
def update_randomize(value):
|
||||
state["randomize"] = value
|
||||
|
||||
center.valueChanged.connect(update_center)
|
||||
span.valueChanged.connect(update_span)
|
||||
step.valueChanged.connect(update_step)
|
||||
randomize.stateChanged.connect(update_randomize)
|
||||
|
||||
|
||||
class _ExplicitScan(LayoutWidget):
|
||||
def __init__(self, state):
|
||||
LayoutWidget.__init__(self)
|
||||
|
|
@ -307,6 +379,7 @@ class ScanEntry(LayoutWidget):
|
|||
self.widgets = OrderedDict()
|
||||
self.widgets["NoScan"] = _NoScan(procdesc, state["NoScan"])
|
||||
self.widgets["RangeScan"] = _RangeScan(procdesc, state["RangeScan"])
|
||||
self.widgets["CenterScan"] = _CenterScan(procdesc, state["CenterScan"])
|
||||
self.widgets["ExplicitScan"] = _ExplicitScan(state["ExplicitScan"])
|
||||
for widget in self.widgets.values():
|
||||
self.stack.addWidget(widget)
|
||||
|
|
@ -314,6 +387,7 @@ class ScanEntry(LayoutWidget):
|
|||
self.radiobuttons = OrderedDict()
|
||||
self.radiobuttons["NoScan"] = QtWidgets.QRadioButton("No scan")
|
||||
self.radiobuttons["RangeScan"] = QtWidgets.QRadioButton("Range")
|
||||
self.radiobuttons["CenterScan"] = QtWidgets.QRadioButton("Center")
|
||||
self.radiobuttons["ExplicitScan"] = QtWidgets.QRadioButton("Explicit")
|
||||
scan_type = QtWidgets.QButtonGroup()
|
||||
for n, b in enumerate(self.radiobuttons.values()):
|
||||
|
|
@ -343,6 +417,8 @@ class ScanEntry(LayoutWidget):
|
|||
"NoScan": {"value": 0.0, "repetitions": 1},
|
||||
"RangeScan": {"start": 0.0, "stop": 100.0*scale, "npoints": 10,
|
||||
"randomize": False},
|
||||
"CenterScan": {"center": 0.*scale, "span": 100.*scale,
|
||||
"step": 10.*scale, "randomize": False},
|
||||
"ExplicitScan": {"sequence": []}
|
||||
}
|
||||
if "default" in procdesc:
|
||||
|
|
@ -361,6 +437,9 @@ class ScanEntry(LayoutWidget):
|
|||
state[ty]["npoints"] = default["npoints"]
|
||||
state[ty]["randomize"] = default["randomize"]
|
||||
state[ty]["seed"] = default["seed"]
|
||||
elif ty == "CenterScan":
|
||||
for key in "center span step randomize seed".split():
|
||||
state[ty][key] = default[key]
|
||||
elif ty == "ExplicitScan":
|
||||
state[ty]["sequence"] = default["sequence"]
|
||||
else:
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ from artiq.language import units
|
|||
|
||||
|
||||
__all__ = ["ScanObject",
|
||||
"NoScan", "RangeScan", "ExplicitScan",
|
||||
"NoScan", "RangeScan", "CenterScan", "ExplicitScan",
|
||||
"Scannable", "MultiScanManager"]
|
||||
|
||||
|
||||
|
|
@ -93,6 +93,43 @@ class RangeScan(ScanObject):
|
|||
"seed": self.seed}
|
||||
|
||||
|
||||
class CenterScan(ScanObject):
|
||||
"""A scan object that yields evenly spaced values within a span around a
|
||||
center. If ``step`` is finite, then ``center`` is always included.
|
||||
Values outside ``span`` around center are never included.
|
||||
If ``randomize`` is True the points are randomly ordered."""
|
||||
def __init__(self, center, span, step, randomize=False, seed=None):
|
||||
self.center = center
|
||||
self.span = span
|
||||
self.step = step
|
||||
self.randomize = randomize
|
||||
self.seed = seed
|
||||
|
||||
if step == 0.:
|
||||
self.sequence = []
|
||||
else:
|
||||
n = 1 + int(span/(2.*step))
|
||||
self.sequence = [center + sign*i*step
|
||||
for i in range(n) for sign in [-1, 1]][1:]
|
||||
|
||||
if randomize:
|
||||
rng = random.Random(seed)
|
||||
random.shuffle(self.sequence, rng.random)
|
||||
|
||||
def __iter__(self):
|
||||
return iter(self.sequence)
|
||||
|
||||
def __len__(self):
|
||||
return len(self.sequence)
|
||||
|
||||
def describe(self):
|
||||
return {"ty": "CenterScan",
|
||||
"center": self.center, "step": self.step,
|
||||
"span": self.span,
|
||||
"randomize": self.randomize,
|
||||
"seed": self.seed}
|
||||
|
||||
|
||||
class ExplicitScan(ScanObject):
|
||||
"""A scan object that yields values from an explicitly defined sequence."""
|
||||
def __init__(self, sequence):
|
||||
|
|
@ -111,6 +148,7 @@ class ExplicitScan(ScanObject):
|
|||
_ty_to_scan = {
|
||||
"NoScan": NoScan,
|
||||
"RangeScan": RangeScan,
|
||||
"CenterScan": CenterScan,
|
||||
"ExplicitScan": ExplicitScan
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -104,18 +104,21 @@ class AD9910Exp(EnvExperiment):
|
|||
self.core.break_realtime()
|
||||
self.dev.cpld.init()
|
||||
self.dev.init()
|
||||
bins = [0]*8
|
||||
self.scan_io_delay(bins)
|
||||
self.set_dataset("bins", bins)
|
||||
self.set_dataset("dly", self.dev.io_update_delay)
|
||||
bins1 = [0]*4
|
||||
bins2 = [0]*4
|
||||
self.scan_io_delay(bins1, bins2)
|
||||
self.set_dataset("bins1", bins1)
|
||||
self.set_dataset("bins2", bins2)
|
||||
self.set_dataset("dly", self.dev.tune_io_update_delay())
|
||||
|
||||
@kernel
|
||||
def scan_io_delay(self, bins):
|
||||
def scan_io_delay(self, bins1, bins2):
|
||||
delay(100*us)
|
||||
n = 100
|
||||
for i in range(n):
|
||||
for phase in range(len(bins)):
|
||||
bins[phase] += self.dev.measure_io_update_alignment(phase)
|
||||
for j in range(len(bins1)):
|
||||
bins1[j] += self.dev.measure_io_update_alignment(j, j + 1)
|
||||
bins2[j] += self.dev.measure_io_update_alignment(j, j + 2)
|
||||
delay(10*ms)
|
||||
|
||||
@kernel
|
||||
|
|
@ -131,6 +134,24 @@ class AD9910Exp(EnvExperiment):
|
|||
sw_off = (self.dev.cpld.sta_read() >> (self.dev.chip_select - 4)) & 1
|
||||
self.set_dataset("sw", (sw_on, sw_off))
|
||||
|
||||
@kernel
|
||||
def profile_readback(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.cpld.init()
|
||||
self.dev.init()
|
||||
for i in range(8):
|
||||
self.dev.set_mu(ftw=i, profile=i)
|
||||
ftw = [0] * 8
|
||||
for i in range(8):
|
||||
self.dev.cpld.set_profile(i)
|
||||
# If PROFILE is not alligned to SYNC_CLK a multi-bit change
|
||||
# doesn't transfer cleanly. Use IO_UPDATE to load the profile
|
||||
# again.
|
||||
self.dev.cpld.io_update.pulse_mu(8)
|
||||
ftw[i] = self.dev.read32(_AD9910_REG_FTW)
|
||||
delay(100*us)
|
||||
self.set_dataset("ftw", ftw)
|
||||
|
||||
|
||||
class AD9910Test(ExperimentCase):
|
||||
def test_instantiate(self):
|
||||
|
|
@ -174,13 +195,19 @@ class AD9910Test(ExperimentCase):
|
|||
def test_io_update_delay(self):
|
||||
self.execute(AD9910Exp, "io_update_delay")
|
||||
dly = self.dataset_mgr.get("dly")
|
||||
bins = self.dataset_mgr.get("bins")
|
||||
print(dly, bins)
|
||||
n = max(bins)
|
||||
# test for 4-periodicity (SYNC_CLK) and maximal contrast
|
||||
for i in range(len(bins)):
|
||||
self.assertEqual(abs(bins[i] - bins[(i + 4) % 8]), n)
|
||||
bins1 = self.dataset_mgr.get("bins1")
|
||||
bins2 = self.dataset_mgr.get("bins2")
|
||||
print(dly, bins1, bins2)
|
||||
n = max(bins2)
|
||||
# no edge at optimal delay
|
||||
self.assertEqual(bins2[(dly + 1) & 3], 0)
|
||||
# edge at expected position
|
||||
self.assertEqual(bins2[(dly + 3) & 3], n)
|
||||
|
||||
def test_sw_readback(self):
|
||||
self.execute(AD9910Exp, "sw_readback")
|
||||
self.assertEqual(self.dataset_mgr.get("sw"), (1, 0))
|
||||
|
||||
def test_profile_readback(self):
|
||||
self.execute(AD9910Exp, "profile_readback")
|
||||
self.assertEqual(self.dataset_mgr.get("ftw"), list(range(8)))
|
||||
|
|
|
|||
|
|
@ -98,6 +98,13 @@ class UrukulExp(EnvExperiment):
|
|||
self.dev.init()
|
||||
self.dev.set_sync_div(2)
|
||||
|
||||
@kernel
|
||||
def profile(self):
|
||||
self.core.break_realtime()
|
||||
self.dev.init()
|
||||
self.dev.set_profile(7)
|
||||
self.dev.set_profile(0)
|
||||
|
||||
|
||||
class UrukulTest(ExperimentCase):
|
||||
def test_instantiate(self):
|
||||
|
|
@ -147,3 +154,6 @@ class UrukulTest(ExperimentCase):
|
|||
|
||||
def test_sync(self):
|
||||
self.execute(UrukulExp, "sync")
|
||||
|
||||
def test_profile(self):
|
||||
self.execute(UrukulExp, "profile")
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ requirements:
|
|||
- python >=3.5.3,<3.6
|
||||
- setuptools 33.1.1
|
||||
- migen 0.8 py35_0+git2d62c0c
|
||||
- misoc 0.11 py35_31+git5ce139dd
|
||||
- misoc 0.11 py35_33+git128750aa
|
||||
- jesd204b 0.10
|
||||
- microscope
|
||||
- binutils-or1k-linux >=2.27
|
||||
|
|
|
|||
|
|
@ -46,4 +46,6 @@ Default network ports
|
|||
+---------------------------------+--------------+
|
||||
| TOPTICA Laser SDK (out-of-tree) | 3272 |
|
||||
+---------------------------------+--------------+
|
||||
| HighFinesse (out-of-tree) | 3273 |
|
||||
+---------------------------------+--------------+
|
||||
|
||||
|
|
|
|||
|
|
@ -131,7 +131,8 @@ On Windows, a third-party tool, `Zadig <http://zadig.akeo.ie/>`_, is necessary.
|
|||
|
||||
1. Make sure the FPGA board's JTAG USB port is connected to your computer.
|
||||
2. Activate Options → List All Devices.
|
||||
3. Select the "Digilent Adept USB Device (Interface 0)" device from the drop-down list.
|
||||
3. Select the "Digilent Adept USB Device (Interface 0)" or "FTDI Quad-RS232 HS" (or similar)
|
||||
device from the drop-down list.
|
||||
4. Select WinUSB from the spinner list.
|
||||
5. Click "Install Driver" or "Replace Driver".
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
{ stdenv, fetchgit, llvm-or1k, makeWrapper, python3, ncurses, zlib, python3Packages }:
|
||||
{ stdenv, fetchFromGitHub, llvm-or1k, makeWrapper, python3, ncurses, zlib, python3Packages }:
|
||||
let
|
||||
version = "0f4ebae";
|
||||
in
|
||||
stdenv.mkDerivation rec {
|
||||
name = "llvmlite-${version}";
|
||||
src = fetchgit {
|
||||
url = "https://github.com/m-labs/llvmlite";
|
||||
src = fetchFromGitHub {
|
||||
rev = "401dfb713166bdd2bc0d3ab2b7ebf12e7a434130";
|
||||
sha256 = "1ci1pnpspv1pqz712yix1nmplq7568vpsr6gzzl3a33w9s0sw2nq";
|
||||
leaveDotGit = true;
|
||||
owner = "m-labs";
|
||||
repo = "llvmlite";
|
||||
sha256 = "1hqahd87ihwgjsaxv0y2iywldi1zgyjxjfy3sy3rr1gnwvxb47xw";
|
||||
};
|
||||
|
||||
buildInputs = [ makeWrapper python3 ncurses zlib llvm-or1k python3Packages.setuptools ];
|
||||
|
|
|
|||
Loading…
Reference in New Issue