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drtio: add timeout on satellite internal CRI buffer space request

pull/1212/head
Sebastien Bourdeauducq 2018-09-05 14:00:09 +08:00
parent 1450e17a73
commit 5f20d79408
4 changed files with 17 additions and 3 deletions
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5
artiq/firmware/satman/main.rs
View File

@ -210,6 +210,9 @@ fn process_errors() {
error!("received truncated packet");
}
if errors & 4 != 0 {
error!("timeout attempting to get buffer space from CRI")
}
if errors & 8 != 0 {
let channel;
let timestamp_event;
let timestamp_counter;
@ -221,7 +224,7 @@ fn process_errors() {
error!("write underflow, channel={}, timestamp={}, counter={}, slack={}",
channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter);
}
if errors & 8 != 0 {
if errors & 16 != 0 {
error!("write overflow");
}
unsafe {

3
artiq/gateware/drtio/rt_errors_satellite.py
View File

@ -8,7 +8,7 @@ from artiq.gateware.rtio.cdc import BlindTransfer
class RTErrorsSatellite(Module, AutoCSR):
def __init__(self, rt_packet, tsc, cri, async_errors):
self.protocol_error = CSR(4)
self.protocol_error = CSR(5)
self.underflow_channel = CSRStatus(16)
self.underflow_timestamp_event = CSRStatus(64)
self.underflow_timestamp_counter = CSRStatus(64)
@ -68,6 +68,7 @@ class RTErrorsSatellite(Module, AutoCSR):
error_csr(self.protocol_error,
(rt_packet.unknown_packet_type, False, None, None),
(rt_packet.packet_truncated, False, None, None),
(rt_packet.buffer_space_timeout, False, None, None),
(underflow, True, underflow_error_cri, underflow_error_csr),
(overflow, True, None, None)
)

10
artiq/gateware/drtio/rt_packet_satellite.py
View File

@ -2,6 +2,7 @@
from migen import *
from migen.genlib.fsm import *
from migen.genlib.misc import WaitTimer
from artiq.gateware.rtio import cri
from artiq.gateware.drtio.rt_serializer import *
@ -13,6 +14,7 @@ class RTPacketSatellite(Module):
self.unknown_packet_type = Signal()
self.packet_truncated = Signal()
self.buffer_space_timeout = Signal()
self.tsc_load = Signal()
self.tsc_load_value = Signal(64)
@ -105,6 +107,9 @@ class RTPacketSatellite(Module):
ongoing_packet = Signal()
self.sync += ongoing_packet.eq(ongoing_packet_next)
timeout_counter = WaitTimer(8191)
self.submodules += timeout_counter
rx_fsm.act("INPUT",
If(rx_dp.frame_r,
rx_dp.packet_buffer_load.eq(1),
@ -149,6 +154,11 @@ class RTPacketSatellite(Module):
NextState("BUFFER_SPACE")
)
rx_fsm.act("BUFFER_SPACE",
timeout_counter.wait.eq(1),
If(timeout_counter.done,
self.buffer_space_timeout.eq(1),
NextState("INPUT")
),
If(self.cri.o_buffer_space_valid,
buffer_space_set.eq(1),
buffer_space_update.eq(1),

2
artiq/gateware/test/drtio/test_full_stack.py
View File

@ -236,7 +236,7 @@ class TestFullStack(unittest.TestCase):
errors = yield from saterr.protocol_error.read()
underflow_channel = yield from saterr.underflow_channel.read()
underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read()
self.assertEqual(errors, 4) # write underflow
self.assertEqual(errors, 8) # write underflow
self.assertEqual(underflow_channel, 42)
self.assertEqual(underflow_timestamp_event, 100)
yield from saterr.protocol_error.write(errors)