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sayma_amc: more fighting with vivado timing analyzer
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parent
94cdad6c1d
commit
2100a8b1f1
@ -326,13 +326,19 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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self.drtio_transceiver.cd_rtio.clk.attr.add("keep")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth.rxoutclk)
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platform.add_false_path_constraints(
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self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
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platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
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self.drtio_transceiver.cd_rtio.clk)
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rtio_channels = []
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for i in range(4):
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