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drtio: rt_packet_satellite CRI fixes
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parent
051bafbfd9
commit
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@ -79,18 +79,25 @@ class RTPacketSatellite(Module):
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]
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# RX FSM
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read = Signal()
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cri_read = Signal()
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cri_buffer_space = Signal()
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self.comb += [
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self.tsc_load_value.eq(
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rx_dp.packet_as["set_time"].timestamp),
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If(load_read_request | read_request_pending,
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If(cri_read | read_request_pending,
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self.cri.chan_sel.eq(
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rx_dp.packet_as["read_request"].chan_sel),
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self.cri.timestamp.eq(
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rx_dp.packet_as["read_request"].timeout)
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).Elif(cri_buffer_space,
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self.cri.chan_sel.eq(
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rx_dp.packet_as["buffer_space_request"].destination << 16)
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).Else(
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self.cri.chan_sel.eq(
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rx_dp.packet_as["write"].chan_sel),
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),
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If(cri_read | read_request_pending,
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self.cri.timestamp.eq(
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rx_dp.packet_as["read_request"].timeout)
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).Else(
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self.cri.timestamp.eq(
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rx_dp.packet_as["write"].timestamp)
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),
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@ -139,8 +146,7 @@ class RTPacketSatellite(Module):
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rx_fsm.act("WRITE",
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If(write_data_buffer_cnt == rx_dp.packet_as["write"].extra_data_cnt,
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self.cri.cmd.eq(cri.commands["write"]),
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NextState("INPUT")
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NextState("WRITE_CMD")
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).Else(
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write_data_buffer_load.eq(1),
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If(~rx_dp.frame_r,
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@ -149,7 +155,17 @@ class RTPacketSatellite(Module):
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)
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)
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)
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rx_fsm.act("WRITE_CMD",
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self.cri.cmd.eq(cri.commands["write"]),
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NextState("INPUT")
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)
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rx_fsm.act("BUFFER_SPACE_REQUEST",
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cri_buffer_space.eq(1),
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NextState("BUFFER_SPACE_REQUEST_CMD")
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)
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rx_fsm.act("BUFFER_SPACE_REQUEST_CMD",
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cri_buffer_space.eq(1),
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self.cri.cmd.eq(cri.commands["get_buffer_space"]),
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NextState("BUFFER_SPACE")
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)
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@ -158,8 +174,7 @@ class RTPacketSatellite(Module):
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If(timeout_counter.done,
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self.buffer_space_timeout.eq(1),
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NextState("INPUT")
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),
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If(self.cri.o_buffer_space_valid,
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).Elif(self.cri.o_buffer_space_valid,
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buffer_space_set.eq(1),
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buffer_space_update.eq(1),
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NextState("INPUT")
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@ -167,7 +182,12 @@ class RTPacketSatellite(Module):
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)
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rx_fsm.act("READ_REQUEST",
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cri_read.eq(1),
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NextState("READ_REQUEST_CMD")
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)
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rx_fsm.act("READ_REQUEST_CMD",
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load_read_request.eq(1),
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cri_read.eq(1),
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self.cri.cmd.eq(cri.commands["read"]),
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NextState("INPUT")
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)
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