mirror of https://github.com/m-labs/artiq.git
rtio/dds: use write-only RT2WB
This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
This commit is contained in:
parent
09141e5bee
commit
c56c0ba41f
|
@ -8,7 +8,7 @@ class AD9914(Module):
|
|||
def __init__(self, pads, nchannels, onehot=False, **kwargs):
|
||||
self.submodules._ll = ClockDomainsRenamer("rio_phy")(
|
||||
ad9_dds.AD9_DDS(pads, **kwargs))
|
||||
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus)
|
||||
self.submodules._rt2wb = RT2WB(len(pads.a)+1, self._ll.bus, write_only=True)
|
||||
self.rtlink = self._rt2wb.rtlink
|
||||
self.probes = [Signal(32) for i in range(nchannels)]
|
||||
|
||||
|
|
Loading…
Reference in New Issue