mirror of
https://github.com/m-labs/artiq.git
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kc705: remove Zotino and Urukul
* use Kasli instead for using EEMs * code required outdated VHDCI adapter 1.0
This commit is contained in:
parent
13984385a8
commit
3168b193e6
@ -119,34 +119,6 @@ device_db = {
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"arguments": {"channel": 26}
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},
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# FMC DIO used to connect to Zotino
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"fmcdio_dirctl_clk": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 27}
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},
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"fmcdio_dirctl_ser": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 28}
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},
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"fmcdio_dirctl_latch": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 29}
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},
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"fmcdio_dirctl": {
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"type": "local",
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"module": "artiq.coredevice.shiftreg",
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"class": "ShiftReg",
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"arguments": {"clk": "fmcdio_dirctl_clk",
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"ser": "fmcdio_dirctl_ser",
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"latch": "fmcdio_dirctl_latch"}
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},
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# DAC
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"spi_ams101": {
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"type": "local",
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@ -160,184 +132,26 @@ device_db = {
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"class": "TTLOut",
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"arguments": {"channel": 20}
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},
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"spi_zotino": {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 30}
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},
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"ttl_zotino_ldac": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 31}
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},
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"dac_zotino": {
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"type": "local",
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"module": "artiq.coredevice.zotino",
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"class": "Zotino",
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"arguments": {
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"spi_device": "spi_zotino",
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"ldac_device": "ttl_zotino_ldac",
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"div_write": 30,
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"div_read": 40
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}
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},
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"spi_urukul": {
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 32}
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},
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"ttl_urukul_io_update": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 33}
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},
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"ttl_urukul_sw0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 35}
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},
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"ttl_urukul_sw1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 36}
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},
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"ttl_urukul_sw2": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 37}
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},
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"ttl_urukul_sw3": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 38}
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},
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"urukul_cpld": {
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"type": "local",
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"module": "artiq.coredevice.urukul",
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"class": "CPLD",
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"arguments": {
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"spi_device": "spi_urukul",
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"io_update_device": "ttl_urukul_io_update",
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"refclk": 100e6
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}
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},
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"urukul_ch0a": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 4,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw0"
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}
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},
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"urukul_ch1a": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 5,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw1"
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}
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},
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"urukul_ch2a": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 6,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw2"
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}
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},
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"urukul_ch3a": {
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"type": "local",
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"module": "artiq.coredevice.ad9912",
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"class": "AD9912",
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"arguments": {
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"pll_n": 10,
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"chip_select": 7,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw3"
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}
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},
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"urukul_ch0b": {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 40,
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"chip_select": 4,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw0"
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}
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},
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"urukul_ch1b": {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 40,
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"chip_select": 5,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw1"
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}
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},
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"urukul_ch2b": {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 40,
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"chip_select": 6,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw2"
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}
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},
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"urukul_ch3b": {
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"type": "local",
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"module": "artiq.coredevice.ad9910",
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"class": "AD9910",
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"arguments": {
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"pll_n": 40,
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"chip_select": 7,
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"cpld_device": "urukul_cpld",
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"sw_device": "ttl_urukul_sw3"
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}
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},
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# AD9914 DDS
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"dds0": {
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"type": "local",
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"module": "artiq.coredevice.ad9914",
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"class": "AD9914",
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"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 0},
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"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 0},
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"comment": "Comments work in DDS panel as well"
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},
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"dds1": {
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"type": "local",
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"module": "artiq.coredevice.ad9914",
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"class": "AD9914",
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"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 1}
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"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 1}
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},
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"dds2": {
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"type": "local",
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"module": "artiq.coredevice.ad9914",
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"class": "AD9914",
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"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 2}
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"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 2}
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},
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# Aliases
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@ -16,8 +16,7 @@ from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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dds, spi2, ad53xx_monitor)
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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from artiq.build_soc import *
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@ -109,99 +108,6 @@ _sdcard_spi_33 = [
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)
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]
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_zotino = [
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("fmcdio_dirctl", 0,
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Subsignal("clk", Pins("HPC:LA32_N")),
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Subsignal("ser", Pins("HPC:LA33_P")),
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Subsignal("latch", Pins("HPC:LA32_P")),
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IOStandard("LVCMOS25")
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),
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("zotino_spi_p", 0,
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Subsignal("clk", Pins("HPC:LA08_P")),
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Subsignal("mosi", Pins("HPC:LA09_P")),
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Subsignal("miso", Pins("HPC:LA10_P")),
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Subsignal("cs_n", Pins("HPC:LA11_P")),
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IOStandard("LVDS_25")
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),
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("zotino_spi_n", 0,
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Subsignal("clk", Pins("HPC:LA08_N")),
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Subsignal("mosi", Pins("HPC:LA09_N")),
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Subsignal("miso", Pins("HPC:LA10_N")),
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Subsignal("cs_n", Pins("HPC:LA11_N")),
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IOStandard("LVDS_25")
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),
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("zotino_ldac", 0,
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Subsignal("p", Pins("HPC:LA13_P")),
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Subsignal("n", Pins("HPC:LA13_N")),
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IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
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)
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]
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# FMC DIO 32ch LVDS a v1.2 on HPC to VHDCI-Carrier v1.1
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# uring the upper/right VHDCI connector: LVDS7 and LVDS8
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# using the lower/left VHDCI connector: LVDS3 and LVDS4
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_urukul = [
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("urukul_spi_p", 0,
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Subsignal("clk", Pins("HPC:LA17_CC_P")),
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Subsignal("mosi", Pins("HPC:LA16_P")),
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Subsignal("miso", Pins("HPC:LA24_P")),
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Subsignal("cs_n", Pins("HPC:LA19_P HPC:LA20_P HPC:LA21_P")),
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IOStandard("LVDS_25"),
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),
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("urukul_spi_n", 0,
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Subsignal("clk", Pins("HPC:LA17_CC_N")),
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Subsignal("mosi", Pins("HPC:LA16_N")),
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Subsignal("miso", Pins("HPC:LA24_N")),
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Subsignal("cs_n", Pins("HPC:LA19_N HPC:LA20_N HPC:LA21_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_io_update", 0,
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Subsignal("p", Pins("HPC:LA22_P")),
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Subsignal("n", Pins("HPC:LA22_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_dds_reset", 0,
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Subsignal("p", Pins("HPC:LA23_P")),
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Subsignal("n", Pins("HPC:LA23_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sync_clk", 0,
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Subsignal("p", Pins("HPC:LA18_CC_P")),
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Subsignal("n", Pins("HPC:LA18_CC_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sync_in", 0,
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Subsignal("p", Pins("HPC:LA25_P")),
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Subsignal("n", Pins("HPC:LA25_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_io_update_ret", 0,
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Subsignal("p", Pins("HPC:LA26_P")),
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Subsignal("n", Pins("HPC:LA26_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw0", 0,
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Subsignal("p", Pins("HPC:LA28_P")),
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Subsignal("n", Pins("HPC:LA28_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw1", 0,
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Subsignal("p", Pins("HPC:LA29_P")),
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Subsignal("n", Pins("HPC:LA29_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw2", 0,
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Subsignal("p", Pins("HPC:LA30_P")),
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Subsignal("n", Pins("HPC:LA30_N")),
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IOStandard("LVDS_25"),
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),
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("urukul_sw3", 0,
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Subsignal("p", Pins("HPC:LA31_P")),
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Subsignal("n", Pins("HPC:LA31_N")),
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IOStandard("LVDS_25"),
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)
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]
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class _StandaloneBase(MiniSoC, AMPSoC):
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@ -243,8 +149,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_ams101_dac)
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self.platform.add_extension(_sdcard_spi_33)
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self.platform.add_extension(_zotino)
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self.platform.add_extension(_urukul)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -340,37 +244,6 @@ class NIST_CLOCK(_StandaloneBase):
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=4))
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fmcdio_dirctl = self.platform.request("fmcdio_dirctl")
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for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
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phy = ttl_simple.Output(s)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"),
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self.platform.request("zotino_spi_n"))
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self.submodules += sdac_phy
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rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
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pads = platform.request("zotino_ldac")
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ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += ldac_phy
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rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
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dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink, ldac_phy.rtlink)
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self.submodules += dac_monitor
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sdac_phy.probes.extend(dac_monitor.probes)
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phy = spi2.SPIMaster(self.platform.request("urukul_spi_p"),
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self.platform.request("urukul_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
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pads = platform.request("urukul_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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@ -68,26 +68,6 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| 21 | LA32_P | Clock |
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+--------------------+-----------------------+--------------+
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| 27 | FMCDIO_DIRCTL_CLK | Output |
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+--------------------+-----------------------+--------------+
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| 28 | FMCDIO_DIRCTL_SER | Output |
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+--------------------+-----------------------+--------------+
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| 29 | FMCDIO_DIRCTL_LATCH | Output |
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+--------------------+-----------------------+--------------+
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| 31 | ZOTINO_LDAC | Output |
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+--------------------+-----------------------+--------------+
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| 33 | URUKUL_IO_UPDATE | Output |
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+--------------------+-----------------------+--------------+
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| 34 | URUKUL_DDS_RESET | Output |
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+--------------------+-----------------------+--------------+
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| 35 | URUKUL_SW0 | Output |
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+--------------------+-----------------------+--------------+
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| 36 | URUKUL_SW1 | Output |
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+--------------------+-----------------------+--------------+
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| 37 | URUKUL_SW2 | Output |
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+--------------------+-----------------------+--------------+
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| 38 | URUKUL_SW3 | Output |
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+--------------------+-----------------------+--------------+
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The board has RTIO SPI buses mapped as follows:
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@ -104,16 +84,9 @@ The board has RTIO SPI buses mapped as follows:
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+--------------+------------------+--------------+--------------+------------+
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| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
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+--------------+------------------+--------------+--------------+------------+
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| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK |
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+--------------+------------------+--------------+--------------+------------+
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| 32 | URUKUL_CS_N[0:2] | URUKUL_MOSI | URUKUL_MISO | URUKUL_CLK |
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+--------------+------------------+--------------+--------------+------------+
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The DDS bus is on channel 39.
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The DDS bus is on channel 27.
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|
||||
This configuration supports a Zotino and/or an Urukul connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0 or rev 1.1. On the VHDCI breakout board, the VHDCI cable to the KC705 should be plugged into to the bottom connector. The EEM cable to the Zotino should be connected to J41 and the EEM cables to Urukul to J42 and J43.
|
||||
|
||||
The shift registers on the FMC card should be configured to set the directions of its LVDS buffers, using :mod:`artiq.coredevice.shiftreg`.
|
||||
|
||||
NIST QC2
|
||||
++++++++
|
||||
|
||||
Loading…
Reference in New Issue
Block a user