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drtio: add buffer space support to rt_packet_repeater
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parent
88b7529d09
commit
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@ -15,7 +15,7 @@ class RTPacketMaster(Module):
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# standard request interface
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#
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# notwrite=1 address=0 buffer space request
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# notwrite=1 address=0 buffer space request <destination>
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# notwrite=1 address=1 read request <channel, timestamp>
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#
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# optimized for write throughput
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@ -252,7 +252,7 @@ class RTPacketMaster(Module):
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)
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)
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tx_fsm.act("BUFFER_SPACE",
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tx_dp.send("buffer_space_request"),
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tx_dp.send("buffer_space_request", destination=sr_channel),
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If(tx_dp.packet_last,
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sr_buf_re.eq(1),
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NextState("IDLE")
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@ -1,14 +1,25 @@
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.misc import WaitTimer
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from artiq.gateware.rtio import cri
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from artiq.gateware.drtio.cdc import CrossDomainNotification
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from artiq.gateware.drtio.rt_serializer import *
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class RTPacketRepeater(Module):
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def __init__(self, link_layer):
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# CRI target interface in rtio domain
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self.cri = cri.Interface()
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# in rtio_rx domain
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self.err_unknown_packet_type = Signal()
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self.err_packet_truncated = Signal()
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# in rtio domain
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self.buffer_space_timeout = Signal()
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# RX/TX datapath
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assert len(link_layer.tx_rt_data) == len(link_layer.rx_rt_data)
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assert len(link_layer.tx_rt_data) % 8 == 0
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@ -61,12 +72,30 @@ class RTPacketRepeater(Module):
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extra_data_counter.eq(1)
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)
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# Buffer space
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buffer_space_destination = Signal(8)
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self.sync.rtio += If(self.cri.cmd == cri.commands["get_buffer_space"],
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buffer_space_destination.eq(self.cri.chan_sel[16:]))
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rx_buffer_space_not = Signal()
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rx_buffer_space = Signal(16)
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buffer_space_not = Signal()
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buffer_space_not_ack = Signal()
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self.submodules += CrossDomainNotification("rtio_rx", "rtio",
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rx_buffer_space_not, rx_buffer_space,
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buffer_space_not, buffer_space_not_ack,
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self.cri.o_buffer_space)
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timeout_counter = WaitTimer(8191)
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self.submodules += timeout_counter
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# TX FSM
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tx_fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE"))
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self.submodules += tx_fsm
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tx_fsm.act("IDLE",
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If(self.cri.cmd == cri.commands["write"], NextState("WRITE"))
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If(self.cri.cmd == cri.commands["write"], NextState("WRITE")),
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If(self.cri.cmd == cri.commands["get_buffer_space"], NextState("BUFFER_SPACE"))
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)
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tx_fsm.act("WRITE",
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tx_dp.send("write",
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@ -90,3 +119,52 @@ class RTPacketRepeater(Module):
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NextState("IDLE")
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)
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)
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tx_fsm.act("BUFFER_SPACE",
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tx_dp.send("buffer_space_request", destination=buffer_space_destination),
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If(tx_dp.packet_last,
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buffer_space_not_ack.eq(1),
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NextState("WAIT_BUFFER_SPACE")
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)
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)
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tx_fsm.act("WAIT_BUFFER_SPACE",
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timeout_counter.wait.eq(1),
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If(timeout_counter.done,
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self.buffer_space_timeout.eq(1),
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NextState("IDLE")
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).Else(
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If(buffer_space_not,
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self.cri.o_buffer_space_valid.eq(1),
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NextState("IDLE")
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),
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)
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)
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# RX FSM
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rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
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self.submodules += rx_fsm
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ongoing_packet_next = Signal()
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ongoing_packet = Signal()
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self.sync.rtio_rx += ongoing_packet.eq(ongoing_packet_next)
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rx_fsm.act("INPUT",
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If(rx_dp.frame_r,
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rx_dp.packet_buffer_load.eq(1),
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If(rx_dp.packet_last,
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Case(rx_dp.packet_type, {
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rx_plm.types["buffer_space_reply"]: NextState("BUFFER_SPACE"),
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"default": self.err_unknown_packet_type.eq(1)
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})
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).Else(
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ongoing_packet_next.eq(1)
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)
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),
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If(~rx_dp.frame_r & ongoing_packet,
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self.err_packet_truncated.eq(1)
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)
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)
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rx_fsm.act("BUFFER_SPACE",
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rx_buffer_space_not.eq(1),
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rx_buffer_space.eq(rx_dp.packet_as["buffer_space_reply"].space),
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NextState("INPUT")
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)
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@ -53,7 +53,7 @@ def get_m2s_layouts(alignment):
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("address", 16),
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("extra_data_cnt", 8),
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("short_data", short_data_len))
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plm.add_type("buffer_space_request")
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plm.add_type("buffer_space_request", ("destination", 8))
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plm.add_type("read_request", ("channel", 16), ("timeout", 64))
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@ -60,3 +60,39 @@ class TestRepeater(unittest.TestCase):
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run_simulation(dut, [send(), pr.receive(receive)])
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self.assertEqual(test_writes, received)
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def test_buffer_space(self):
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for nwords in range(1, 8):
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pt, pr, dut = create_dut(nwords)
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def send_requests():
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for i in range(10):
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yield dut.cri.chan_sel.eq(i << 16)
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yield dut.cri.cmd.eq(cri.commands["get_buffer_space"])
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yield
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yield dut.cri.cmd.eq(cri.commands["nop"])
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yield
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while not (yield dut.cri.o_buffer_space_valid):
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yield
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buffer_space = yield dut.cri.o_buffer_space
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self.assertEqual(buffer_space, 2*i)
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current_request = None
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@passive
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def send_replies():
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nonlocal current_request
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while True:
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while current_request is None:
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yield
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yield from pt.send("buffer_space_reply", space=2*current_request)
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current_request = None
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def receive(packet_type, field_dict, trailer):
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nonlocal current_request
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self.assertEqual(packet_type, "buffer_space_request")
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self.assertEqual(trailer, [])
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self.assertEqual(current_request, None)
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current_request = field_dict["destination"]
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run_simulation(dut, [send_requests(), send_replies(), pr.receive(receive)])
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