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kasli: use 150MHz for DRTIO by default (Sayma compatibility)

pull/1234/head
Sebastien Bourdeauducq 2019-01-02 23:03:57 +08:00
parent cc58318500
commit ab9ca0ee0a
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/targets/kasli.py
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@ -810,7 +810,7 @@ class _MasterBase(MiniSoC, AMPSoC):
}
mem_map.update(MiniSoC.mem_map)
def __init__(self, rtio_clk_freq=125e6, **kwargs):
def __init__(self, rtio_clk_freq=150e6, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
@ -959,7 +959,7 @@ class _SatelliteBase(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, rtio_clk_freq=125e6, **kwargs):
def __init__(self, rtio_clk_freq=150e6, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",