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https://github.com/m-labs/artiq.git
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kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target
Urukul sync is not reliable at 125/1000
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@ -5,7 +5,7 @@ device_db = {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 1e-9}
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"arguments": {"host": core_addr, "ref_period": 1.25e-9}
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},
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"core_log": {
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"type": "controller",
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@ -49,9 +49,9 @@ device_db.update({
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})
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sync_delay_seeds = [
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[17, 17, 16, 16],
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[16, 15, 17, 20],
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[18, 19, 20, 20],
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[15, 15, 15, 16],
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[14, 15, 16, 16],
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[18, 18, 20, 19],
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]
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io_update_delays = [
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@ -112,7 +112,7 @@ for j in range(3):
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"spi_device": "spi_urukul{}".format(j),
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"sync_device": "ttl_urukul{}_sync".format(j),
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"io_update_device": "ttl_urukul{}_io_update".format(j),
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"refclk": 125e6,
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"refclk": 100e6,
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"clk_sel": 2
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}
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}
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@ -125,6 +125,7 @@ for j in range(3):
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"class": "AD9910",
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"arguments": {
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"pll_n": 32,
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"pll_vco": 4,
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"chip_select": 4 + i,
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"cpld_device": "urukul{}_cpld".format(j),
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"sw_device": "ttl_urukul{}_sw{}".format(j, i),
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@ -179,7 +180,7 @@ device_db.update(
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"arguments": {
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"spi_device": "spi_urukul3",
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"io_update_device": "ttl_urukul3_io_update",
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"refclk": 125e6,
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"refclk": 100e6,
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"clk_sel": 0
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}
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}
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@ -176,8 +176,8 @@ fn setup_si5324_as_synthesizer()
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bwsel : 3,
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crystal_ref: true
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};
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// 100MHz output, from crystal (reference for HMC830)
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#[cfg(si5324_sayma_ref)]
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// 100MHz output, from crystal. Also used as reference for Sayma HMC830.
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#[cfg(any(si5324_sayma_ref, all(rtio_frequency = "100.0", not(si5324_ext_ref))))]
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const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
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= board_artiq::si5324::FrequencySettings {
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n1_hs : 9,
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@ -541,7 +541,7 @@ class Berkeley(_StandaloneBase):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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self.config["RTIO_FREQUENCY"] = "100.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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