cri: fix routing table depth

2018-09-12 17:30:55 +08:00 · 2018-09-12 17:30:55 +08:00 · 5bcd40ff59
parent edf403b837
commit 5bcd40ff59
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/rtio/cri.py
+++ b/artiq/gateware/rtio/cri.py
@ -130,7 +130,7 @@ class CRIDecoder(Module, AutoCSR):
        selected = Signal(slave_bits)

        if enable_routing:
-            self.specials.routing_table = Memory(slave_bits, 8)
+            self.specials.routing_table = Memory(slave_bits, 256)

            rtp_csr = self.routing_table.get_port(write_capable=True)
            self.specials += rtp_csr