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jesd204: update core to v0.10

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Closes #727
Closes #1127
This commit is contained in:
Sebastien Bourdeauducq 2018-08-17 22:50:07 +08:00
parent 5c3e834c4d
commit 041dc0f64a
2 changed files with 6 additions and 7 deletions
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11
artiq/gateware/jesd204_tools.py
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@ -85,12 +85,11 @@ class UltrascaleTX(Module, AutoCSR):
phy.transmitter.cd_tx.clk)
phys.append(phy)
to_jesd = ClockDomainsRenamer("jesd")
self.submodules.core = core = to_jesd(JESD204BCoreTX(
phys, settings, converter_data_width=64))
self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
core.register_jsync(platform.request("dac_sync", dac))
core.register_jref(jesd_crg.jref)
self.submodules.core = JESD204BCoreTX(
phys, settings, converter_data_width=64)
self.submodules.control = JESD204BCoreTXControl(self.core)
self.core.register_jsync(platform.request("dac_sync", dac))
self.core.register_jref(jesd_crg.jref)
# This assumes:

2
conda/artiq-dev/meta.yaml
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@ -16,7 +16,7 @@ requirements:
- setuptools 33.1.1
- migen 0.7 py35_73+gitbef9dea
- misoc 0.11 py35_29+git57ebe119
- jesd204b 0.9
- jesd204b 0.10
- microscope
- binutils-or1k-linux >=2.27
- llvm-or1k 6.0.0