M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

kasli: add false path between RTIO and CL clocks

This commit is contained in:
Sebastien Bourdeauducq 2018-07-21 13:26:13 +08:00
parent 031de58d21
commit 3638a966e1
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/gateware/targets/kasli.py
View File

@ -299,6 +299,8 @@ class MITLL(_StandaloneBase):
self.add_rtio(self.rtio_channels)
self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group)
self.platform.add_false_path_constraints(
self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
class USTC(_StandaloneBase):
@ -338,6 +340,8 @@ class USTC(_StandaloneBase):
self.add_rtio(self.rtio_channels)
self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group)
self.platform.add_false_path_constraints(
self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
class Tsinghua(_StandaloneBase):
@ -374,6 +378,8 @@ class Tsinghua(_StandaloneBase):
self.add_rtio(self.rtio_channels)
self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group)
self.platform.add_false_path_constraints(
self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
class WIPM(_StandaloneBase):
@ -543,6 +549,8 @@ class LUH(_StandaloneBase):
self.add_rtio(self.rtio_channels)
self.config["HAS_GRABBER"] = None
self.add_csr_group("grabber", self.grabber_csr_group)
self.platform.add_false_path_constraints(
self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
class Tester(_StandaloneBase):