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artiq
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compiler,gateware: atomic now stores

pull/1204/head
Sebastien Bourdeauducq 2018-12-02 05:06:46 +08:00
parent fd00021a52
commit 7e14f3ca4e
3 changed files with 22 additions and 19 deletions
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26
artiq/compiler/transforms/llvm_ir_generator.py
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@ -149,10 +149,6 @@ class LLVMIRGenerator:
self.tbaa_tree,
ll.Constant(lli64, 1)
])
self.tbaa_now = self.llmodule.add_metadata([
ll.MetaDataString(self.llmodule, "timeline position"),
self.tbaa_tree
])
def needs_sret(self, lltyp, may_be_large=True):
if isinstance(lltyp, ll.VoidType):
@ -1152,20 +1148,30 @@ class LLVMIRGenerator:
return self.map(insn.operands[0])
elif insn.op == "now_mu":
llnow = self.llbuilder.load(self.llbuiltin("now"), name=insn.name)
llnow.set_metadata("tbaa", self.tbaa_now)
return llnow
elif insn.op == "at_mu":
time, = insn.operands
return self.llbuilder.store(self.map(time), self.llbuiltin("now"))
lltime = self.map(time)
lltime_hi = self.llbuilder.trunc(self.llbuilder.lshr(lltime, ll.Constant(lli64, 32)), lli32)
lltime_lo = self.llbuilder.trunc(lltime, lli32)
llnow_hiptr = self.llbuilder.bitcast(self.llbuiltin("now"), lli32.as_pointer())
llnow_loptr = self.llbuilder.gep(llnow_hiptr, [self.llindex(1)])
llstore_hi = self.llbuilder.store_atomic(lltime_hi, llnow_hiptr, ordering="seq_cst", align=4)
llstore_lo = self.llbuilder.store_atomic(lltime_lo, llnow_loptr, ordering="seq_cst", align=4)
return llstore_lo
elif insn.op == "delay_mu":
interval, = insn.operands
llnowptr = self.llbuiltin("now")
llnow = self.llbuilder.load(llnowptr, name="now.old")
llnow.set_metadata("tbaa", self.tbaa_now)
lladjusted = self.llbuilder.add(llnow, self.map(interval), name="now.new")
llnowstore = self.llbuilder.store(lladjusted, llnowptr)
llnowstore.set_metadata("tbaa", self.tbaa_now)
return llnowstore
lladjusted_hi = self.llbuilder.trunc(self.llbuilder.lshr(lladjusted, ll.Constant(lli64, 32)), lli32)
lladjusted_lo = self.llbuilder.trunc(lladjusted, lli32)
llnow_hiptr = self.llbuilder.bitcast(llnowptr, lli32.as_pointer())
llnow_loptr = self.llbuilder.gep(llnow_hiptr, [self.llindex(1)])
llstore_hi = self.llbuilder.store_atomic(lladjusted_hi, llnow_hiptr, ordering="seq_cst", align=4)
llstore_lo = self.llbuilder.store_atomic(lladjusted_lo, llnow_loptr, ordering="seq_cst", align=4)
return llstore_lo
elif insn.op == "watchdog_set":
interval, = insn.operands
return self.llbuilder.call(self.llbuiltin("watchdog_set"), [self.map(interval)])

13
artiq/gateware/rtio/cri.py
View File

@ -87,18 +87,15 @@ class KernelInitiator(Module, AutoCSR):
# # #
now_lo_backing = Signal(32)
now_hi_backing = Signal(32)
now = Signal(64, reset_less=True)
self.sync += [
# TODO: fix compiler and make atomic
#If(self.now_lo.re, now_lo_backing.eq(self.now_lo.r)),
#If(self.now_hi.re, now.eq(Cat(now_lo_backing, self.now_hi.r)))
If(self.now_lo.re, now[:32].eq(self.now_lo.r)),
If(self.now_hi.re, now[32:].eq(self.now_hi.r))
If(self.now_hi.re, now_hi_backing.eq(self.now_hi.r)),
If(self.now_lo.re, now.eq(Cat(self.now_lo.r, now_hi_backing)))
]
self.comb += [
self.now_lo.w.eq(now[:32]),
self.now_hi.w.eq(now[32:])
self.now_hi.w.eq(now[32:]),
self.now_lo.w.eq(now[:32])
]
self.comb += [

2
conda/artiq-dev/meta.yaml
View File

@ -20,7 +20,7 @@ requirements:
- microscope
- binutils-or1k-linux >=2.27
- llvm-or1k 6.0.0
- llvmlite-artiq 0.23.0.dev py35_4
- llvmlite-artiq 0.23.0.dev py35_5
- rust-core-or1k 1.28.0 21
- openocd 0.10.0 6
- lit