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sayma: simplify Ultrascale LVDS T false path 

Recommended by Xilinx.
pull/1259/head
Sebastien Bourdeauducq 2019-01-25 23:40:48 +08:00
parent 359fb1f207
commit 9966e789fc
1 changed files with 1 additions and 2 deletions
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3
artiq/gateware/targets/sayma_amc.py
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@ -299,8 +299,7 @@ def workaround_us_lvds_tristate(platform):
# See:
# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
platform.add_platform_command(
"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]"
" -through [get_pins -filter {{REF_PIN_NAME == O}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
class Master(MiniSoC, AMPSoC):