M-Labs
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artiq
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sayma: add back Urukul and Zotino

This commit is contained in:
Sebastien Bourdeauducq 2018-07-18 10:27:54 +08:00
parent 5e62910a8d
commit 25170a53e5
2 changed files with 5 additions and 5 deletions
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8
artiq/gateware/targets/sayma_amc.py
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@ -474,12 +474,12 @@ class Master(MiniSoC, AMPSoC):
phy = ttl_simple.Output(s)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
#eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
# iostandard="LVDS")
eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
iostandard="LVDS")
#eem.Zotino.add_std(self, 3, ttl_simple.Output,
# iostandard="LVDS")
eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
iostandard="LVDS")
eem.Zotino.add_std(self, 3, ttl_simple.Output,
iostandard="LVDS")
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

2
conda/artiq-dev/meta.yaml
View File

@ -15,7 +15,7 @@ requirements:
- python >=3.5.3,<3.6
- setuptools 33.1.1
- migen 0.7 py35_73+gitbef9dea
- misoc 0.11 py35_27+git37dfced7
- misoc 0.11 py35_29+git57ebe119
- jesd204b 0.7
- microscope
- binutils-or1k-linux >=2.27