mirror of https://github.com/m-labs/artiq.git
grabber: only advance when DVAL
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@ -85,10 +85,12 @@ class Parser(Module, AutoCSR):
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self.sync.cl += [
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last_lval.eq(lval),
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last_fval.eq(fval),
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pix.x.eq(pix.x + 1),
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If(dval,
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pix.x.eq(pix.x + 1),
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),
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If(~lval,
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pix.x.eq(0),
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If(last_lval, last_x.eq(pix.x)),
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pix.x.eq(0),
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If(last_fval & last_lval,
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pix.y.eq(pix.y + 1)
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)
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