mirror of https://github.com/m-labs/artiq.git
kasli: lower RTIO clock jitter
* high bandwidth since the si5324 is good * no low power ibufgds * drop bufg between ibufgds and pll * increase pll vco frequency to 1.5 GHz Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -34,13 +34,11 @@ class _RTIOCRG(Module, AutoCSR):
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clk_synth = platform.request("si5324_clkout_fabric")
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clk_synth_se = Signal()
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clk_synth_buffered = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="TRUE",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_buffered),
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]
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pll_locked = Signal()
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@ -50,21 +48,21 @@ class _RTIOCRG(Module, AutoCSR):
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=clk_synth_buffered,
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i_CLKIN2=clk_synth_se,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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# VCO @ 1.5GHz when using 125MHz input
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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