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add missing files
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55
artiq/gateware/drtio/cdc.py
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55
artiq/gateware/drtio/cdc.py
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from migen import *
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from migen.genlib.cdc import PulseSynchronizer
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class CrossDomainRequest(Module):
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def __init__(self, domain,
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req_stb, req_ack, req_data,
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srv_stb, srv_ack, srv_data):
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dsync = getattr(self.sync, domain)
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request = PulseSynchronizer("sys", domain)
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reply = PulseSynchronizer(domain, "sys")
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self.submodules += request, reply
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ongoing = Signal()
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self.comb += request.i.eq(~ongoing & req_stb)
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self.sync += [
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req_ack.eq(reply.o),
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If(req_stb, ongoing.eq(1)),
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If(req_ack, ongoing.eq(0))
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]
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if req_data is not None:
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req_data_r = Signal.like(req_data)
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req_data_r.attr.add("no_retiming")
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self.sync += If(req_stb, req_data_r.eq(req_data))
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dsync += [
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If(request.o, srv_stb.eq(1)),
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If(srv_ack, srv_stb.eq(0))
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]
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if req_data is not None:
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dsync += If(request.o, srv_data.eq(req_data_r))
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self.comb += reply.i.eq(srv_stb & srv_ack)
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class CrossDomainNotification(Module):
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def __init__(self, domain, rdomain,
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emi_stb, emi_data,
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rec_stb, rec_ack, rec_data):
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emi_data_r = Signal(len(emi_data))
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emi_data_r.attr.add("no_retiming")
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dsync = getattr(self.sync, domain)
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dsync += If(emi_stb, emi_data_r.eq(emi_data))
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ps = PulseSynchronizer(domain, rdomain)
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self.submodules += ps
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self.comb += ps.i.eq(emi_stb)
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rsync = getattr(self.sync, rdomain)
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rsync += [
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If(rec_ack, rec_stb.eq(0)),
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If(ps.o,
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rec_data.eq(emi_data_r),
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rec_stb.eq(1)
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)
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]
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48
artiq/gateware/rtio/tsc.py
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48
artiq/gateware/rtio/tsc.py
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from migen import *
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from artiq.gateware.rtio.cdc import GrayCodeTransfer
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class TSC(Module):
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def __init__(self, mode, glbl_fine_ts_width=0):
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self.glbl_fine_ts_width = glbl_fine_ts_width
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# in rtio domain
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self.coarse_ts = Signal(64 - glbl_fine_ts_width)
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self.full_ts = Signal(64)
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# in sys domain
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# monotonic, may lag behind the counter in the IO clock domain, but
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# not be ahead of it.
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self.coarse_ts_sys = Signal.like(self.coarse_ts)
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self.full_ts_sys = Signal(64)
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# in rtio domain
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self.load = Signal()
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self.load_value = Signal.like(self.coarse_ts)
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if mode == "async":
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self.full_ts_cri = self.full_ts_sys
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elif mode == "sync":
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self.full_ts_cri = self.full_ts
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else:
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raise ValueError
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# # #
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self.sync.rtio += If(self.load,
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self.coarse_ts.eq(self.load_value)
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).Else(
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self.coarse_ts.eq(self.coarse_ts + 1)
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)
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coarse_ts_cdc = GrayCodeTransfer(len(self.coarse_ts)) # from rtio to sys
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self.submodules += coarse_ts_cdc
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self.comb += [
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coarse_ts_cdc.i.eq(self.coarse_ts),
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self.coarse_ts_sys.eq(coarse_ts_cdc.o)
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]
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self.comb += [
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self.full_ts.eq(self.coarse_ts << glbl_fine_ts_width),
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self.full_ts_sys.eq(self.coarse_ts_sys << glbl_fine_ts_width)
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]
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