mirror of https://github.com/m-labs/artiq.git
drtio: add TSC sync and missed command detection to rt_packet_repeater
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@ -18,8 +18,16 @@ class RTPacketRepeater(Module):
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self.err_packet_truncated = Signal()
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# in rtio domain
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self.command_missed = Signal()
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self.buffer_space_timeout = Signal()
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# set_time interface, in rtio domain
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self.set_time_stb = Signal()
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self.set_time_ack = Signal()
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self.tsc_value = Signal(64)
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# # #
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# RX/TX datapath
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assert len(link_layer.tx_rt_data) == len(link_layer.rx_rt_data)
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assert len(link_layer.tx_rt_data) % 8 == 0
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@ -33,6 +41,11 @@ class RTPacketRepeater(Module):
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link_layer.rx_rt_frame, link_layer.rx_rt_data, rx_plm))
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self.submodules += rx_dp
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# TSC sync
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tsc_value = Signal(64)
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tsc_value_load = Signal()
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self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value))
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# Write buffer and extra data count
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wb_timestamp = Signal(64)
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wb_chan_sel = Signal(24)
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@ -89,13 +102,30 @@ class RTPacketRepeater(Module):
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timeout_counter = ClockDomainsRenamer("rtio")(WaitTimer(8191))
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self.submodules += timeout_counter
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# Missed commands
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cri_ready = Signal()
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self.sync.rtio += self.command_missed.eq(~cri_ready & (self.cri.cmd != cri.commands["nop"]))
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# TX FSM
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tx_fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE"))
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self.submodules += tx_fsm
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tx_fsm.act("IDLE",
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If(self.cri.cmd == cri.commands["write"], NextState("WRITE")),
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If(self.cri.cmd == cri.commands["get_buffer_space"], NextState("BUFFER_SPACE"))
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If(self.set_time_stb,
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tsc_value_load.eq(1),
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NextState("SET_TIME")
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).Else(
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cri_ready.eq(1),
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If(self.cri.cmd == cri.commands["write"], NextState("WRITE")),
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If(self.cri.cmd == cri.commands["get_buffer_space"], NextState("BUFFER_SPACE"))
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)
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)
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tx_fsm.act("SET_TIME",
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tx_dp.send("set_time", timestamp=tsc_value),
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If(tx_dp.packet_last,
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self.set_time_ack.eq(1),
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NextState("IDLE")
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)
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)
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tx_fsm.act("WRITE",
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tx_dp.send("write",
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@ -19,6 +19,32 @@ def create_dut(nwords):
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class TestRepeater(unittest.TestCase):
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def test_set_time(self):
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nwords = 2
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pt, pr, dut = create_dut(nwords)
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def send():
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yield dut.tsc_value.eq(0x12345678)
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yield dut.set_time_stb.eq(1)
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while not (yield dut.set_time_ack):
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yield
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yield dut.set_time_stb.eq(0)
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yield
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for _ in range(30):
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yield
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received = False
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def receive(packet_type, field_dict, trailer):
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nonlocal received
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self.assertEqual(packet_type, "set_time")
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self.assertEqual(trailer, [])
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self.assertEqual(field_dict["timestamp"], 0x12345678)
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self.assertEqual(received, False)
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received = True
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run_simulation(dut, [send(), pr.receive(receive)])
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self.assertEqual(received, True)
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def test_output(self):
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test_writes = [
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(1, 10, 21, 0x42),
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