M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity
8,301 Commits 13 Branches 35 Tags 26 MiB
Commit Graph

1563 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq b8968262d7 Merge branch 'syncrtio' 2023-01-12 16:44:54 +08:00
Sebastien Bourdeauducq 514ac953ce remove obsolete SI5324_AS_SYNTHESIZER config option 2023-01-12 13:01:08 +08:00
mwojcik 70edc9c5c6 test_write_underflow: decrease underflow delay 2023-01-11 12:02:51 +08:00
mwojcik 9042426872 echo test: add two more yields 2023-01-11 12:02:51 +08:00
mwojcik cd860beda2 test_full_stack: restore missing check_ttls 2023-01-11 12:02:51 +08:00
mwojcik 627504b60e test_dma: remove redundant clock 2023-01-11 12:02:51 +08:00
mwojcik eb3742fb08 kc705: do not reset si5324 during clock switch 2023-01-09 18:18:21 +08:00
Sebastien Bourdeauducq 63f1a6d197 drtio: partially fix tests 2023-01-06 18:33:13 +08:00
Sebastien Bourdeauducq ec893222a4 rtio: remove support for async mode 2023-01-06 18:22:05 +08:00
Sebastien Bourdeauducq 573a895c1e remove RTIOClockMultiplier 2023-01-06 17:59:18 +08:00
Sebastien Bourdeauducq cf2a4972f7 remove WRPLL 2023-01-06 17:53:11 +08:00
Sebastien Bourdeauducq 5da9794895 remove Sayma and Metlino support 2023-01-06 17:41:12 +08:00
Spaqin 3838dfc1d1
DRTIO: RTIO/SYS clock merge, KC705 2023-01-06 07:13:38 +08:00
Spaqin 17efc28dbe
DRTIO: RTIO/SYS clock merge 2022-12-17 15:39:54 +08:00
mwojcik ad000609ce simplify tsc with no rtio/sys clk distinction 2022-11-01 08:12:54 +08:00
mwojcik f8eb695c0f dma test: no more rsys or rtio domains 2022-11-01 08:12:54 +08:00
mwojcik 458bd8a927 kasli_generic: remove rtio clockdomain reference 2022-11-01 08:12:54 +08:00
mwojcik a6856a5e4a rtio: remove rtio clock, use sys instead 2022-11-01 08:12:54 +08:00
mwojcik 1eb87164be kasli: remove rtiocrg, use rtio/sys merge 2022-11-01 08:12:54 +08:00
Robert Jördens 1820e1f715 phaser: cleanup 2022-10-19 16:25:33 +02:00
Robert Jördens af28bf3550 simplify dt reset 2022-09-08 08:39:48 +02:00
Robert Jördens a91836e5fe easier fix for dt 2022-09-06 20:26:50 +00:00
Robert Jördens 27e3c044ed fix dt computation 2022-09-06 14:32:57 +00:00
Robert Jördens 3809ac5470 fix type, clean clear 2022-09-02 19:47:06 +00:00
Robert Jördens 0df2cadcd3 fixes 2022-09-02 15:29:36 +00:00
Robert Jördens 25c0dc4688 whitespace 2022-09-02 14:54:18 +00:00
Robert Jördens cf48232a90 fixes 2022-09-02 14:38:38 +00:00
Robert Jördens a20087848d differentiate phaser modes 2022-09-02 11:03:23 +00:00
Robert Jördens 31663556b8 phaser: add miqro mode 2022-09-02 09:32:06 +00:00
Robert Jördens 47f90a58cc add miqro phy 2022-09-02 09:32:06 +00:00
Mikołaj Sowiński 3c7ab498d1 Added DDS selection for Kasli tester variant 
Signed-off-by: Mikołaj Sowiński <msowinski@technosystem.com.pl>
 2022-09-02 17:14:23 +08:00
cc78078 3535d0f1ae
kasli: relocate the SatelliteBase Error LED code (#1955) 2022-08-12 12:41:50 +08:00
cc78078 185c91f522
kasli: add Error LED to MasterBase and SatelliteBase 2022-08-11 15:06:58 +08:00
Alex Wong Tat Hang a3ae82502c
gtx_7series: fix IBUFGS_GTE2 buffer parameters 
Co-authored-by: topquark12 <aw@m-labs.hk>
 2022-08-01 10:21:28 +08:00
Spaqin 8be945d5c7
Urukul monitoring (#1142, #1921) 2022-07-07 10:52:53 +08:00
Spaqin 35f30ddf05
Expose TTLClockGen for Kasli JSONs (#1886) 2022-05-06 13:33:42 +08:00
Leon Riesebos c4292770f8
Kasli JSON description for SPI over DIO cards (#1800) 2022-02-26 07:36:00 +08:00
Peter Drmota 4eee49f889 gateware.test.suservo: Fix tests for python >=3.7 
Closes #1748
 2022-01-11 17:16:09 +08:00
occheung 9eee0e5a7b gateware/suservo: fix profile no. in test 
Follow-up/Test update for 9d49302.
 2022-01-11 14:20:47 +08:00
occheung cea0a15e1e suservo: use default urukul profile 2022-01-10 16:21:39 +08:00
occheung 9d493028e5 gateware/suservo: write to profile 7 
Fixes #1817.
 2022-01-07 16:41:19 +08:00
mwojcik 7953f3d705 kc705: add drtio 100mhz clk switch 2021-12-03 17:19:11 +08:00
mwojcik f281112779 satman: add 100mhz si5324 settings 
siphaser: add calculated vco for 100mhz comment
 2021-12-03 17:19:11 +08:00
mwojcik eec3ea6589 siphaser: add support for 100mhz rtio 2021-12-03 17:19:11 +08:00
Etienne Wodey 9f830b86c0
kasli: add SED lanes count option to HW description JSON file (#1745) 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-12-03 17:05:35 +08:00
Peter Drmota 20e079a381
AD9910 driver feature extension and SUServo IIR readability (#1500) 
* coredevice.ad9910: Add set_cfr2 function and extend arguments of set_cfr1 and set_sync

* SUServo: Wrap CPLD and DDS devices in a list

* SUServo: Refactor [nfc]

Co-authored-by: drmota <peter.drmota@physics.ox.ac.uk>
Co-authored-by: David Nadlinger <code@klickverbot.at>
 2021-11-15 12:09:16 +08:00
occheung 09945ecc4d gateware: fix drtio/dma tests 2021-11-08 16:59:08 +08:00
occheung cb247f235f gateware: pass adr_w/data_w to submodules 2021-11-08 16:59:08 +08:00
occheung 90f944481c kernel_cpu: add fpu if not kasli v1.x 2021-11-08 16:59:08 +08:00
occheung d84ad0095b comm_cpu: select 64b bus if not kasli v1.x 2021-11-08 16:59:08 +08:00