mirror of https://github.com/m-labs/artiq.git
rtio: refactor TSC to allow sharing between cores
This commit is contained in:
parent
0fe2a6801e
commit
f3fe818049
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@ -5,7 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio import cri, rtlink
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from artiq.gateware.rtio.sed.core import *
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from artiq.gateware.rtio.input_collector import *
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from artiq.gateware.drtio import (link_layer, aux_controller,
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@ -47,32 +47,33 @@ async_errors_layout = [
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class SyncRTIO(Module):
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def __init__(self, channels, fine_ts_width=3, lane_count=8, fifo_depth=128):
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def __init__(self, tsc, channels, lane_count=8, fifo_depth=128):
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self.cri = cri.Interface()
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self.async_errors = Record(async_errors_layout)
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self.coarse_ts = Signal(64 - fine_ts_width)
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self.comb += self.cri.counter.eq(self.coarse_ts << fine_ts_width)
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chan_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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for channel in channels),
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max(rtlink.get_fine_ts_width(channel.interface.i)
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for channel in channels))
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assert tsc.glbl_fine_ts_width >= chan_fine_ts_width
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self.submodules.outputs = ClockDomainsRenamer("rio")(
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SED(channels, fine_ts_width, "sync",
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SED(channels, tsc.glbl_fine_ts_width, "sync",
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lane_count=lane_count, fifo_depth=fifo_depth,
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enable_spread=False, report_buffer_space=True,
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interface=self.cri))
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self.comb += self.outputs.coarse_timestamp.eq(self.coarse_ts)
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self.sync.rtio += self.outputs.minimum_coarse_timestamp.eq(self.coarse_ts + 16)
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self.comb += self.outputs.coarse_timestamp.eq(tsc.coarse_ts)
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self.sync.rtio += self.outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 16)
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self.submodules.inputs = ClockDomainsRenamer("rio")(
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InputCollector(channels, fine_ts_width, "sync",
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interface=self.cri))
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self.comb += self.inputs.coarse_timestamp.eq(self.coarse_ts)
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InputCollector(tsc, channels, "sync", interface=self.cri))
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for attr, _ in async_errors_layout:
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self.comb += getattr(self.async_errors, attr).eq(getattr(self.outputs, attr))
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class DRTIOSatellite(Module):
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def __init__(self, chanif, rx_synchronizer=None, fine_ts_width=3):
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def __init__(self, tsc, chanif, rx_synchronizer=None):
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self.reset = CSRStorage(reset=1)
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self.reset_phy = CSRStorage(reset=1)
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self.tsc_loaded = CSR()
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@ -127,13 +128,10 @@ class DRTIOSatellite(Module):
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rt_packet_satellite.RTPacketSatellite(link_layer_sync, interface=self.cri))
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self.comb += self.rt_packet.reset.eq(self.cd_rio.rst)
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self.coarse_ts = Signal(64 - fine_ts_width)
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self.sync.rtio += \
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If(self.rt_packet.tsc_load,
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self.coarse_ts.eq(self.rt_packet.tsc_load_value)
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).Else(
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self.coarse_ts.eq(self.coarse_ts + 1)
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)
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self.comb += [
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tsc.load.eq(self.rt_packet.tsc_load),
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tsc.load_value.eq(self.rt_packet.tsc_load_value)
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]
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ps_tsc_load = PulseSynchronizer("rtio", "sys")
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self.submodules += ps_tsc_load
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@ -144,7 +142,7 @@ class DRTIOSatellite(Module):
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]
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self.submodules.rt_errors = rt_errors_satellite.RTErrorsSatellite(
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self.rt_packet, self.cri, self.async_errors)
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self.rt_packet, tsc, self.cri, self.async_errors)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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@ -156,7 +154,7 @@ class DRTIOSatellite(Module):
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class DRTIOMaster(Module):
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def __init__(self, chanif, fine_ts_width=3):
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def __init__(self, tsc, chanif):
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self.submodules.link_layer = link_layer.LinkLayer(
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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@ -164,7 +162,7 @@ class DRTIOMaster(Module):
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_master.RTPacketMaster(self.link_layer)
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self.submodules.rt_controller = rt_controller_master.RTController(
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self.rt_packet, fine_ts_width)
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tsc, self.rt_packet)
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self.submodules.rt_manager = rt_controller_master.RTManager(self.rt_packet)
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self.submodules.aux_controller = aux_controller.AuxController(
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@ -7,7 +7,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.cdc import GrayCodeTransfer
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from artiq.gateware.rtio import cri
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@ -26,26 +25,8 @@ class _CSRs(AutoCSR):
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self.o_wait = CSRStatus()
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class RTIOCounter(Module):
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def __init__(self, width):
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self.width = width
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# Timestamp counter in RTIO domain
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self.value_rtio = Signal(width)
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# Timestamp counter resynchronized to sys domain
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# Lags behind value_rtio, monotonic and glitch-free
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self.value_sys = Signal(width)
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# # #
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# note: counter is in rtio domain and never affected by the reset CSRs
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self.sync.rtio += self.value_rtio.eq(self.value_rtio + 1)
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gt = GrayCodeTransfer(width)
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self.submodules += gt
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self.comb += gt.i.eq(self.value_rtio), self.value_sys.eq(gt.o)
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class RTController(Module):
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def __init__(self, rt_packet, fine_ts_width):
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def __init__(self, tsc, rt_packet):
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self.csrs = _CSRs()
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self.cri = cri.Interface()
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@ -80,11 +61,9 @@ class RTController(Module):
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self.comb += self.csrs.protocol_error.w.eq(
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Cat(err_unknown_packet_type, err_packet_truncated, err_buffer_space_timeout))
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# master RTIO counter and counter synchronization
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self.submodules.counter = RTIOCounter(64-fine_ts_width)
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# TSC synchronization
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self.comb += [
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self.cri.counter.eq(self.counter.value_sys << fine_ts_width),
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rt_packet.tsc_value.eq(self.counter.value_rtio),
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rt_packet.tsc_value.eq(tsc.coarse_ts),
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self.csrs.set_time.w.eq(rt_packet.set_time_stb)
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]
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self.sync += [
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@ -130,8 +109,8 @@ class RTController(Module):
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self.submodules += timeout_counter
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cond_underflow = Signal()
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self.comb += cond_underflow.eq((self.cri.timestamp[fine_ts_width:]
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- self.csrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
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self.comb += cond_underflow.eq((self.cri.timestamp[tsc.glbl_fine_ts_width:]
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- self.csrs.underflow_margin.storage[tsc.glbl_fine_ts_width:]) < tsc.coarse_ts_sys)
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buffer_space = Signal(16)
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@ -7,7 +7,7 @@ from artiq.gateware.rtio.cdc import BlindTransfer
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class RTErrorsSatellite(Module, AutoCSR):
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def __init__(self, rt_packet, cri, async_errors):
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def __init__(self, rt_packet, tsc, cri, async_errors):
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self.protocol_error = CSR(4)
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self.underflow_channel = CSRStatus(16)
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self.underflow_timestamp_event = CSRStatus(64)
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@ -60,7 +60,7 @@ class RTErrorsSatellite(Module, AutoCSR):
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overflow.eq(cri.o_status[0]),
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underflow_error_cri.eq(Cat(cri.chan_sel[:16],
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cri.timestamp,
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cri.counter)),
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tsc.full_ts_cri)),
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Cat(self.underflow_channel.status,
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self.underflow_timestamp_event.status,
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self.underflow_timestamp_counter.status).eq(underflow_error_csr)
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@ -1,3 +1,4 @@
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from artiq.gateware.rtio.tsc import TSC
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from artiq.gateware.rtio.cri import KernelInitiator, CRIInterconnectShared
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from artiq.gateware.rtio.channel import Channel, LogChannel
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from artiq.gateware.rtio.core import Core
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@ -14,8 +14,7 @@ from artiq.gateware.rtio.input_collector import *
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class Core(Module, AutoCSR):
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def __init__(self, channels, lane_count=8, fifo_depth=128,
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glbl_fine_ts_width=None):
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def __init__(self, tsc, channels, lane_count=8, fifo_depth=128):
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self.cri = cri.Interface()
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self.reset = CSR()
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self.reset_phy = CSR()
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@ -61,36 +60,23 @@ class Core(Module, AutoCSR):
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for channel in channels),
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max(rtlink.get_fine_ts_width(channel.interface.i)
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for channel in channels))
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if glbl_fine_ts_width is None:
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glbl_fine_ts_width = chan_fine_ts_width
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assert glbl_fine_ts_width >= chan_fine_ts_width
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coarse_ts = Signal(64-glbl_fine_ts_width)
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self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
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coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) # from rtio to sys
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self.submodules += coarse_ts_cdc
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self.comb += [
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coarse_ts_cdc.i.eq(coarse_ts),
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self.cri.counter.eq(coarse_ts_cdc.o << glbl_fine_ts_width)
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]
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self.coarse_ts = coarse_ts
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assert tsc.glbl_fine_ts_width >= chan_fine_ts_width
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# Outputs/Inputs
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quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]
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outputs = SED(channels, glbl_fine_ts_width, "async",
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outputs = SED(channels, tsc.glbl_fine_ts_width, "async",
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quash_channels=quash_channels,
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lane_count=lane_count, fifo_depth=fifo_depth,
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interface=self.cri)
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self.submodules += outputs
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self.comb += outputs.coarse_timestamp.eq(coarse_ts)
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self.sync += outputs.minimum_coarse_timestamp.eq(coarse_ts_cdc.o + 16)
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self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
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self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts_sys + 16)
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inputs = InputCollector(channels, glbl_fine_ts_width, "async",
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inputs = InputCollector(tsc, channels, "async",
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quash_channels=quash_channels,
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interface=self.cri)
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self.submodules += inputs
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self.comb += inputs.coarse_timestamp.eq(coarse_ts)
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# Asychronous output errors
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o_collision_sync = BlindTransfer(data_width=16)
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@ -49,11 +49,6 @@ layout = [
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# <3:link error>
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# <0> and <1> are mutually exclusive. <1> has higher priority.
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("i_status", 4, DIR_S_TO_M),
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# value of the timestamp counter transferred into the CRI clock domain.
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# monotonic, may lag behind the counter in the IO clock domain, but
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# not be ahead of it.
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("counter", 64, DIR_S_TO_M)
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]
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@ -63,8 +58,10 @@ class Interface(Record):
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class KernelInitiator(Module, AutoCSR):
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def __init__(self, cri=None):
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def __init__(self, tsc, cri=None):
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self.chan_sel = CSRStorage(24)
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# monotonic, may lag behind the counter in the IO clock domain, but
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# not be ahead of it.
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self.timestamp = CSRStorage(64)
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# Writing timestamp clears o_data. This implements automatic
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@ -109,7 +106,7 @@ class KernelInitiator(Module, AutoCSR):
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self.o_data.dat_w.eq(0),
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self.o_data.we.eq(self.timestamp.re),
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]
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self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))
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self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
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class CRIDecoder(Module):
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@ -24,11 +24,10 @@ def get_channel_layout(coarse_ts_width, interface):
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class InputCollector(Module):
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def __init__(self, channels, glbl_fine_ts_width, mode, quash_channels=[], interface=None):
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def __init__(self, tsc, channels, mode, quash_channels=[], interface=None):
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if interface is None:
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interface = cri.Interface()
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self.cri = interface
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self.coarse_timestamp = Signal(64 - glbl_fine_ts_width)
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# # #
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@ -55,7 +54,7 @@ class InputCollector(Module):
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continue
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# FIFO
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layout = get_channel_layout(len(self.coarse_timestamp), iif)
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layout = get_channel_layout(len(tsc.coarse_ts), iif)
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fifo = fifo_factory(layout_len(layout), channel.ififo_depth)
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self.submodules += fifo
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fifo_in = Record(layout)
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@ -67,10 +66,10 @@ class InputCollector(Module):
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# FIFO write
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if iif.delay:
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counter_rtio = Signal.like(self.coarse_timestamp, reset_less=True)
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sync_io += counter_rtio.eq(self.coarse_timestamp - (iif.delay + 1))
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counter_rtio = Signal.like(tsc.coarse_ts, reset_less=True)
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sync_io += counter_rtio.eq(tsc.coarse_ts - (iif.delay + 1))
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else:
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counter_rtio = self.coarse_timestamp
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counter_rtio = tsc.coarse_ts
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if hasattr(fifo_in, "data"):
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self.comb += fifo_in.data.eq(iif.data)
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if hasattr(fifo_in, "timestamp"):
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@ -130,7 +129,7 @@ class InputCollector(Module):
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self.cri.i_data.eq(Array(i_datas)[sel]),
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self.cri.i_timestamp.eq(Array(i_timestamps)[sel]),
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),
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If((self.cri.counter >= input_timeout) | (i_status_raw != 0),
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If((tsc.full_ts_cri >= input_timeout) | (i_status_raw != 0),
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If(input_pending, i_ack.eq(1)),
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input_pending.eq(0)
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),
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@ -52,9 +52,11 @@ class DUT(Module):
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self.ttl1 = Signal()
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self.transceivers = DummyTransceiverPair(nwords)
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self.submodules.master = DRTIOMaster(self.transceivers.alice,
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fine_ts_width=0)
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self.submodules.master_ki = rtio.KernelInitiator(self.master.cri)
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self.submodules.tsc_master = rtio.TSC("async")
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self.submodules.master = DRTIOMaster(self.tsc_master,
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self.transceivers.alice)
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self.submodules.master_ki = rtio.KernelInitiator(self.tsc_master,
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self.master.cri)
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self.master.rt_controller.csrs.link_up.storage.reset = 1
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rx_synchronizer = DummyRXSynchronizer()
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@ -66,16 +68,16 @@ class DUT(Module):
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rtio.Channel.from_phy(self.phy1),
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rtio.Channel.from_phy(self.phy2),
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]
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self.submodules.tsc_satellite = rtio.TSC("sync")
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self.submodules.satellite = DRTIOSatellite(
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self.transceivers.bob, rx_synchronizer, fine_ts_width=0)
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self.tsc_satellite, self.transceivers.bob, rx_synchronizer)
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self.satellite.reset.storage.reset = 0
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self.satellite.reset.storage_full.reset = 0
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self.satellite.reset_phy.storage.reset = 0
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self.satellite.reset_phy.storage_full.reset = 0
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self.submodules.satellite_rtio = SyncRTIO(
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rtio_channels, fine_ts_width=0, lane_count=4, fifo_depth=8)
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self.tsc_satellite, rtio_channels, lane_count=4, fifo_depth=8)
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self.comb += [
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self.satellite_rtio.coarse_ts.eq(self.satellite.coarse_ts),
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self.satellite.cri.connect(self.satellite_rtio.cri),
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self.satellite.async_errors.eq(self.satellite_rtio.async_errors),
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]
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@ -106,7 +108,7 @@ class OutputsTestbench:
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def sync(self):
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t = self.now + 15
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while (yield self.dut.master.cri.counter) < t:
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while (yield self.dut.tsc_master.full_ts_cri) < t:
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yield
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def write(self, channel, data):
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@ -127,7 +127,8 @@ class FullStackTB(Module):
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self.submodules.memory = wishbone.SRAM(
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256, init=sequence, bus=bus)
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self.submodules.dut = dma.DMA(bus)
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self.submodules.rtio = rtio.Core(rtio_channels)
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self.submodules.tsc = rtio.TSC("async")
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self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
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self.comb += self.dut.cri.connect(self.rtio.cri)
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@ -38,9 +38,8 @@ class DUT(Module):
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rtio.Channel.from_phy(self.phy0, ififo_depth=4),
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rtio.Channel.from_phy(self.phy1, ififo_depth=4)
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]
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self.submodules.input_collector = InputCollector(rtio_channels, 0, "sync")
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self.sync += self.input_collector.coarse_timestamp.eq(self.input_collector.coarse_timestamp + 1)
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self.comb += self.input_collector.cri.counter.eq(self.input_collector.coarse_timestamp)
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self.submodules.tsc = ClockDomainsRenamer({"rtio": "sys"})(rtio.TSC("sync"))
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self.submodules.input_collector = InputCollector(self.tsc, rtio_channels, "sync")
|
||||
|
||||
@property
|
||||
def cri(self):
|
||||
|
|
Loading…
Reference in New Issue