mirror of https://github.com/m-labs/artiq.git
drtio: support external IBUFDS_GTE3
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8b8e1844f0
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@ -636,13 +636,17 @@ class GTH(Module, TransceiverInterface):
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# # #
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refclk = Signal()
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ibufds_ceb = Signal()
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self.specials += Instance("IBUFDS_GTE3",
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i_CEB=ibufds_ceb,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk)
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create_buf = hasattr(clock_pads, "p")
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if create_buf:
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refclk = Signal()
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ibufds_ceb = Signal()
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self.specials += Instance("IBUFDS_GTE3",
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i_CEB=ibufds_ceb,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk)
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else:
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refclk = clock_pads
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rtio_tx_clk = Signal()
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channel_interfaces = []
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@ -665,10 +669,11 @@ class GTH(Module, TransceiverInterface):
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self.submodules.tx_phase_alignment = GTHTXPhaseAlignement(self.gths)
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TransceiverInterface.__init__(self, channel_interfaces)
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# GTH PLLs recover on their own from an interrupted clock input,
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# but be paranoid about HMC7043 noise.
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self.stable_clkin.storage.attr.add("no_retiming")
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self.comb += ibufds_ceb.eq(~self.stable_clkin.storage)
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if create_buf:
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# GTH PLLs recover on their own from an interrupted clock input,
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# but be paranoid about HMC7043 noise.
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self.stable_clkin.storage.attr.add("no_retiming")
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self.comb += ibufds_ceb.eq(~self.stable_clkin.storage)
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self.comb += [
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self.cd_rtio.clk.eq(self.gths[master].cd_rtio_tx.clk),
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