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sayma: pass rtio_clk_freq to DDMTD core

pull/1259/head
Sebastien Bourdeauducq 2019-01-29 15:00:49 +08:00
parent 90c9fa446f
commit 9ae57fd51e
1 changed files with 4 additions and 2 deletions
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6
artiq/gateware/targets/sayma_amc.py
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@ -282,7 +282,8 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(platform.request("adc_sysref"))
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(
platform.request("adc_sysref"), rtio_clk_freq)
self.csr_devices.append("sysref_ddmtd")
platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
self.sysref_ddmtd.cd_helper.clk)
@ -577,7 +578,8 @@ class Satellite(BaseSoC, RTMCommon):
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(platform.request("adc_sysref"))
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(
platform.request("adc_sysref"), rtio_clk_freq)
self.csr_devices.append("sysref_ddmtd")
platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
self.sysref_ddmtd.cd_helper.clk)