Sebastien Bourdeauducq
37d0a5dc19
rtio/ttl: expose OE
2019-10-16 18:48:20 +08:00
Sebastien Bourdeauducq
bc060b7f01
style
2019-10-16 18:18:11 +08:00
Sebastien Bourdeauducq
21a1c6de3f
sayma: use SFP0 for DRTIO master
2019-10-16 17:53:40 +08:00
Sebastien Bourdeauducq
314d9b5d06
kasli: default to 125MHz frequency for DRTIO
...
This is the consistent and most common option. Sayma will also eventually move to it.
2019-10-08 12:59:52 +08:00
Sebastien Bourdeauducq
4df2c5d1fb
sayma: prepare for SYSREF align
...
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
2019-10-08 12:30:47 +08:00
Sebastien Bourdeauducq
03007b896e
sayma_amc: sma -> mcx
2019-10-07 20:31:35 +08:00
Sebastien Bourdeauducq
97a0dee3e8
jesd204: remove ibuf_disable
...
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
2019-10-06 22:26:31 +08:00
Sebastien Bourdeauducq
f8e4cc37d0
sayma_rtm: reset and detect DACs
2019-10-06 20:15:27 +08:00
Sebastien Bourdeauducq
f62dc7e1d4
sayma: refactor JESD DAC channel groups
2019-10-06 20:15:09 +08:00
Sebastien Bourdeauducq
1c6c22fde9
sayma_amc: HMC830_REF moved to RTM side
2019-10-06 18:15:37 +08:00
Sebastien Bourdeauducq
e6ff44301b
sayma_amc: cleanup (v2.0 only)
2019-10-06 18:11:43 +08:00
Sebastien Bourdeauducq
e9b81f6e33
remove serwb
...
DRTIO is a better solution
2019-10-06 18:10:23 +08:00
Sebastien Bourdeauducq
7cd02d30b7
sayma_rtm_drtio: replace sayma_rtm
2019-10-06 17:59:53 +08:00
Sebastien Bourdeauducq
b3b85135a3
sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase
2019-10-06 17:59:11 +08:00
Sebastien Bourdeauducq
346c985347
sayma_rtm_drtio: use artiq_sayma folder
2019-10-06 17:30:08 +08:00
Sebastien Bourdeauducq
4198033657
sayma_rtm_drtio: cleanup (v2.0 only)
2019-10-06 16:42:34 +08:00
Sebastien Bourdeauducq
5612b31860
sayma_rtm_drtio: add HMC clock chip and DAC control
2019-10-06 16:15:24 +08:00
Sebastien Bourdeauducq
a8cf4c2b18
sayma_rtm: hwrev v2.0 by default
2019-10-06 13:25:30 +08:00
Sebastien Bourdeauducq
bb5ff46f7d
Merge branch 'wrpll'
2019-10-05 10:24:11 +08:00
Sebastien Bourdeauducq
7b95814cf5
sayma_amc: refactor, add SimpleSatellite variant
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
58b7bdcecc
sayma_amc: refactor RTM FPGA code
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
96fc4a21e8
sayma_amc: remove dummy FPGA pin assignment testing code
2019-10-05 10:24:06 +08:00
Sebastien Bourdeauducq
6aa68e1715
sayma_rtm2: select filtered clock from Si5324
2019-10-04 22:56:16 +08:00
Sebastien Bourdeauducq
6cb0f5de59
sayma_amc: enable DRTIO switching
2019-10-04 22:55:23 +08:00
Sebastien Bourdeauducq
0cf8a46bbd
sayma_amc2: select filtered clock from Si5324
2019-10-04 21:28:26 +08:00
Robert Jördens
f0e87d2e59
grabber: remove unused code
2019-09-20 15:26:12 +02:00
Sebastien Bourdeauducq
991c686d72
kasli_generic,eem: print RTIO channels in hex like artiq_ddb_template
2019-09-11 15:51:53 +08:00
Sebastien Bourdeauducq
7492a59f6d
kasli_generic: add SUServo support ( #1343 )
2019-09-11 11:12:48 +08:00
Sebastien Bourdeauducq
21021beb08
kasli: remove opticlock (moved to kasli_generic)
2019-09-09 15:03:10 +08:00
Sebastien Bourdeauducq
cfb5ef5548
kasli_generic: add Novogorny support
2019-09-09 14:54:34 +08:00
Sebastien Bourdeauducq
1fb317778a
eem/grabber: allow third EEM to be specified
2019-08-29 18:58:12 +08:00
Sebastien Bourdeauducq
959679d8b7
wrpll: add I2CMasterMachine
2019-08-27 18:02:05 +08:00
Sebastien Bourdeauducq
1fd2322662
wrpll/thls: implement global writeback
2019-08-15 23:16:17 +08:00
Sebastien Bourdeauducq
24082b687e
wrpll/filters: clean up and make compatible with thls
2019-08-15 17:58:22 +08:00
Sebastien Bourdeauducq
9331fafab0
wrpll/filters: new code from Weida
2019-08-15 17:24:40 +08:00
Sebastien Bourdeauducq
5c3974c265
wrpll/thls: fix opcode decoding
2019-08-15 17:12:48 +08:00
Sebastien Bourdeauducq
19620948bf
wrpll/thls: implement signed numbers
2019-08-15 17:04:17 +08:00
Sebastien Bourdeauducq
efc43142a6
wrpll/thls: implement min/max
2019-08-15 16:42:59 +08:00
Sebastien Bourdeauducq
44969b03ad
wrpll/thls: rework instruction decoding
2019-08-15 15:55:13 +08:00
Sebastien Bourdeauducq
2776c5b16b
wrpll/thls: support mulshift
2019-08-15 15:07:13 +08:00
Sebastien Bourdeauducq
f861459ace
wrpll: add filter algorithms (WIP)
2019-08-02 13:23:16 +08:00
Sebastien Bourdeauducq
7a5dcbe60e
wrpll/thls: support processor start/stop
2019-07-24 18:51:33 +08:00
Sebastien Bourdeauducq
623446f82c
wrpll/thls: simple simulation demo
2019-07-20 18:50:57 +08:00
Sebastien Bourdeauducq
831b3514d3
wrpll/thls: stop at return statement
2019-07-19 16:27:29 +08:00
Sebastien Bourdeauducq
34222b3f38
wrpll: encode thls program
2019-07-09 17:56:14 +08:00
Sebastien Bourdeauducq
5f461d08cd
wrpll: add simple thls compiler
2019-07-09 16:07:31 +08:00
Sebastien Bourdeauducq
e4fff390a8
si590 -> si549
...
Had mistaken the part numbers.
2019-07-07 09:39:55 +08:00
Sebastien Bourdeauducq
dceb5ae501
wrpll: Si590 I2C mux, CDC
2019-07-05 23:42:37 +08:00
Sebastien Bourdeauducq
f8dba7ae35
rtio: use BlindTransfer from Migen
2019-07-05 18:46:18 +08:00
David Nadlinger
0353966ef7
gateware/suservo: Sign-extend data on RTIO read-back
...
See GitHub #1327 for original patch by Brad Bondurant.
2019-06-14 23:46:16 +01:00
David Nadlinger
720838a23e
gateware/suservo: Avoid magic number for activation delay width
...
Mostly for documentation purposes; 8 bits ought to be enough for
everyone.
2019-06-14 23:45:40 +01:00
Sebastien Bourdeauducq
43e58c939c
sayma: drop MasterDAC
...
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.
Now Sayma works fine with Kasli as a master, which is simpler.
2019-06-14 14:06:16 +08:00
Sebastien Bourdeauducq
b04e15741b
drop SI5324_SAYMA_REF
2019-06-14 14:03:48 +08:00
Sebastien Bourdeauducq
bc2cfd77f5
metlino: add EEMs
2019-05-19 18:16:00 +08:00
Sebastien Bourdeauducq
cdef50c0dd
sayma_amc: Urukul v1.3
2019-05-19 16:54:38 +08:00
Sebastien Bourdeauducq
9dcaae6395
metlino: use variant output directory
2019-05-19 16:24:51 +08:00
Sebastien Bourdeauducq
b4779969d0
metlino: work around vivado bug ( #1230 )
2019-05-19 11:27:27 +08:00
Sebastien Bourdeauducq
874542f33f
add Metlino support
2019-05-19 10:57:43 +08:00
hartytp
cfe1f56f73
suservo: add some more comments to the RTServoMem to clarify the RTIO interface ( #1323 )
2019-05-17 16:12:35 +01:00
Sebastien Bourdeauducq
fda3cb2482
kasli_generic: add edge counter support
2019-05-09 17:19:11 +08:00
Robert Jördens
ead9a42842
kasli: remove VLBAIMaster, VLBAISatellite variants
2019-05-08 15:58:25 +00:00
Robert Jördens
0c9b810501
kasli: remove PTB/PTB2/LUH/HUB variants
...
see sinara-systems and nix-scripts repos
2019-05-08 15:51:18 +00:00
Robert Jördens
1d2cc60e0d
kasli_generic: support ext_ref
2019-05-08 15:51:18 +00:00
David Nadlinger
4d215cf541
firmware: Add Si5324 config for 125 MHz ext ref
...
PLL divider settings as suggested by DSPLLsim 5.1.
2019-04-15 22:22:19 +01:00
Sebastien Bourdeauducq
97b7ed557b
sayma_amc: do not use SFP0 (now used for Ethernet)
2019-04-12 18:47:18 +08:00
Chris Ballance
4499ef1748
kasli: only add moninj core if there are probes to monitor
2019-03-24 14:09:52 +08:00
Sebastien Bourdeauducq
5d31cf2268
sayma_rtm2: si5324_clkout -> cdr_clk_clean
2019-03-23 13:48:36 +08:00
Sebastien Bourdeauducq
560849e693
sayma_amc: add DRTIO transceiver on rtm_amc_link for v2 hardware
2019-03-23 13:41:22 +08:00
Sebastien Bourdeauducq
bbb8c00518
sayma_amc: default to satellite variant
2019-03-23 13:37:55 +08:00
Sebastien Bourdeauducq
18fbe0b081
sayma_rtm_drtio: support v2 hardware
2019-03-23 13:31:28 +08:00
Sebastien Bourdeauducq
c7205ad82f
sayma_rtm: preliminary v2 support
2019-03-23 12:37:03 +08:00
Sebastien Bourdeauducq
33b28f6e56
sayma_amc: add placeholder code to use DDMTD signals on v2 hardware
2019-03-21 17:37:22 +08:00
Sebastien Bourdeauducq
2ec5a58c59
sayma_amc: si5324_clkout -> cdr_clk_clean
2019-03-21 14:09:33 +08:00
Sebastien Bourdeauducq
e47ba4b35e
kasli_generic: fix identifier string
2019-03-08 19:57:20 +08:00
Sebastien Bourdeauducq
62c7f75a9e
sayma_amc: support hardware revisions
2019-02-25 23:49:45 +08:00
Sebastien Bourdeauducq
d45249197c
siphaser: improve ultrascale clock routing
2019-02-25 23:00:01 +08:00
Sebastien Bourdeauducq
de3992bbdd
kasli: remove HUST variants (supported by kasli_generic)
2019-02-23 15:44:17 +08:00
Sebastien Bourdeauducq
791f830ef6
kasli_generic: support DRTIO
2019-02-23 15:41:05 +08:00
Sebastien Bourdeauducq
1c35c051a5
kasli: remove variants supported by generic builder
2019-02-22 23:08:49 +08:00
Sebastien Bourdeauducq
8edc2318ab
style
2019-02-22 17:19:20 +08:00
Sebastien Bourdeauducq
6ad2e13515
kasli: add generic builder (WIP)
2019-02-12 19:18:09 +08:00
Sebastien Bourdeauducq
ff4e4f15ed
kasli: expose base SoC classes
2019-02-12 18:33:27 +08:00
Sebastien Bourdeauducq
1cfd26dc2e
kasli: add UNSW variant
2019-02-08 17:51:51 +08:00
Sebastien Bourdeauducq
3e8fe3f29d
suservo: fix permissions
2019-02-08 14:54:02 +08:00
hartytp
87e85bcc14
suservo: fix coefficient data writing
...
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 14:47:11 +01:00
Sebastien Bourdeauducq
b56c7cec1e
kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target
...
Urukul sync is not reliable at 125/1000
2019-02-05 11:24:45 +08:00
Sebastien Bourdeauducq
ea431b6982
sayma_rtm: use 150MHz RTIO freq for DDMTD
2019-01-31 20:43:44 +08:00
Sebastien Bourdeauducq
ec230d6560
sayma: move SYSREF DDMTD to the RTM
...
Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
Sebastien Bourdeauducq
8119000982
sayma_rtm_drtio: use Si5324 soft reset
...
Needs easy board rework to cut trace at pin 1 of Si5324.
The Si5324 contains an internal pull-up on that pin.
Allows using Si5324 + HMC7043 chips at the same time.
Allows the Si5324 bypass hack for DDMTD experiments on the RTM.
2019-01-31 19:43:54 +08:00
Sebastien Bourdeauducq
d3c608aaec
jesd204sync: reset and check lock status of DDMTD helper PLL in firmware
2019-01-31 15:11:16 +08:00
Sebastien Bourdeauducq
c591009220
sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler
...
Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
2019-01-29 23:30:01 +08:00
Sebastien Bourdeauducq
9ae57fd51e
sayma: pass rtio_clk_freq to DDMTD core
2019-01-29 15:06:45 +08:00
Sebastien Bourdeauducq
47312e55d3
sayma: set RTIO_FREQUENCY in MasterDAC
2019-01-28 13:43:28 +08:00
Sebastien Bourdeauducq
443d6d8688
sayma_amc: pass RTIO clock frequency to SiPhaser
2019-01-28 09:49:03 +08:00
Sebastien Bourdeauducq
81b0046f98
ddmtd: add deglitchers
2019-01-27 20:38:41 +08:00
Sebastien Bourdeauducq
8632b553d2
ddmtd: use IOB register to sample input
2019-01-27 09:50:02 +08:00
Sebastien Bourdeauducq
9966e789fc
sayma: simplify Ultrascale LVDS T false path
...
Recommended by Xilinx.
2019-01-25 23:40:48 +08:00
Sebastien Bourdeauducq
359fb1f207
sayma: fix DDMTD STA
2019-01-25 23:39:19 +08:00
Sebastien Bourdeauducq
cb04230f86
sayma: SYSREF setup/hold validation demonstration
...
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
2019-01-25 16:58:58 +08:00
Sebastien Bourdeauducq
3356717316
sayma: DDMTD SYSREF measurement demonstration
2019-01-25 16:00:31 +08:00
Sebastien Bourdeauducq
4941fb3300
sayma: 2.4GHz DAC clocking (4X interpolation)
...
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
Sebastien Bourdeauducq
07b5b0d36d
kasli: adapt Master target to new hardware
2019-01-24 18:27:15 +08:00
Sebastien Bourdeauducq
154269b77a
kasli: fix HUST satellite Urukul
2019-01-23 17:59:43 +08:00
Sebastien Bourdeauducq
d7e6f104d2
kasli: add HUST variants
2019-01-23 14:11:51 +08:00
Sebastien Bourdeauducq
81f2b2c864
kasli: remove unpopulated Tester EEMs
...
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
2019-01-23 12:14:44 +08:00
Sebastien Bourdeauducq
9ee5fea88d
kasli: support optional SATA port for DRTIO
2019-01-22 18:06:48 +08:00
Sebastien Bourdeauducq
bff8c8cb05
kasli: add Berkeley variant
2019-01-21 17:44:17 +08:00
Sebastien Bourdeauducq
a2ff2cc173
sayma_amc: use more selective IOBUFDS false path
2019-01-19 11:47:50 +08:00
David Nadlinger
1c71ae636a
examples: Add edge counters to kasli_tester variant
...
This enables test_edge_counter on the CI system.
2019-01-15 10:55:07 +00:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
Sebastien Bourdeauducq
4cb9f77fd8
sayma_amc: fix Master timing constraints
2019-01-13 13:53:07 +08:00
Sebastien Bourdeauducq
9b213b17af
sayma_amc: forward RTM UART in Master variant as well
2019-01-09 18:57:57 +08:00
Sebastien Bourdeauducq
c7b18952b8
sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad
2019-01-09 13:47:08 +08:00
Sebastien Bourdeauducq
3217488824
add Sayma RTM DRTIO target
2019-01-07 00:13:47 +08:00
Sebastien Bourdeauducq
66b3132c28
sayma_amc: fix RTIO TSC instantiation
2019-01-06 14:54:32 +08:00
Sebastien Bourdeauducq
cf9447ab77
rtio/cri: remove unneeded CSR management
2019-01-05 23:40:45 +08:00
Sebastien Bourdeauducq
2100a8b1f1
sayma_amc: more fighting with vivado timing analyzer
2019-01-05 12:25:30 +08:00
Sebastien Bourdeauducq
62d7c89c48
sayma_amc: use high-resolution TTL on SMAs ( #792 )
2019-01-03 20:50:38 +08:00
Sebastien Bourdeauducq
0972d61e81
ttl_serdes_ultrascale: use GTH clock domains
2019-01-03 20:50:04 +08:00
Sebastien Bourdeauducq
f007895fad
drtio/gth_ultrascale: fix rtiox clock domain
2019-01-03 20:49:38 +08:00
Sebastien Bourdeauducq
10ebf63c47
jesd204_tools: get the Vivado timing analyzer to behave
2019-01-03 20:22:35 +08:00
Sebastien Bourdeauducq
4af8fd6a0d
ttl_serdes_ultrascale: fix Input
2019-01-03 20:14:54 +08:00
Sebastien Bourdeauducq
175f8b8ccc
drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT ( #792 )
2019-01-03 20:14:18 +08:00
Sebastien Bourdeauducq
77126ce5b3
kasli: use hwrev 1.1 by default for DRTIO examples
2019-01-02 23:04:20 +08:00
Sebastien Bourdeauducq
ab9ca0ee0a
kasli: use 150MHz for DRTIO by default (Sayma compatibility)
2019-01-02 23:03:57 +08:00
Sebastien Bourdeauducq
cc58318500
siphaser: autocalibrate skew using RX synchronizer
...
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
2019-01-02 22:29:27 +08:00
Sebastien Bourdeauducq
f5cda3689e
sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant
2019-01-02 16:46:16 +08:00
Robert Jördens
6df4ae934f
eem: name the servo submodule
...
This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos
close #1201
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
Sebastien Bourdeauducq
7e14f3ca4e
compiler,gateware: atomic now stores
2018-12-02 05:06:46 +08:00
Sebastien Bourdeauducq
c56c0ba41f
rtio/dds: use write-only RT2WB
...
This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
2018-11-26 07:38:15 +08:00
Sebastien Bourdeauducq
09141e5bee
rtio/wishbone: support write-only interface
2018-11-26 07:38:06 +08:00
Sebastien Bourdeauducq
450a035f9e
suservo: move overflowing RTIO address bits into data
2018-11-26 06:54:20 +08:00
Sebastien Bourdeauducq
ae8ef18f47
rtlink: sanity-check parameters
2018-11-26 01:14:02 +08:00
Sebastien Bourdeauducq
53e79f553f
Merge branch 'master' into new
2018-11-19 11:54:50 +08:00
Sebastien Bourdeauducq
78d4b3a7da
gateware/targets: expose variant lists
...
This allows writing scripts that build all variants.
2018-11-17 22:10:20 +08:00
Sebastien Bourdeauducq
1b841805f6
Merge branch 'master' into new
2018-11-16 15:20:32 +08:00
Robert Jördens
2af6edb8f5
eem: fix reset/sync in suservo
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-13 13:00:54 +00:00
Sebastien Bourdeauducq
1f7858b80b
test/dsp: fix rtio_output
2018-11-09 22:11:44 +08:00
Sebastien Bourdeauducq
e509ab8553
test/dsp: use absolute import path
...
Avoids "ImportError: attempted relative import with no known parent package"
when doing a simple "python -m unittest test_XXX.py".
2018-11-09 22:10:46 +08:00
Sebastien Bourdeauducq
c990b5e4f1
Merge remote-tracking branch 'origin/master' into new
2018-11-08 20:21:56 +08:00
Sebastien Bourdeauducq
f74dda639f
drtio: 8-bit address
2018-11-08 18:36:20 +08:00
Sebastien Bourdeauducq
8caea0e6d3
gateware,runtime: optimize RTIO kernel interface further
...
* now pinning (TODO: atomicity)
* for inputs, merge request and timeout registers
2018-11-08 18:29:24 +08:00
Sebastien Bourdeauducq
aadf5112b7
rtio: remove incorrect comment
2018-11-08 00:02:44 +08:00
Sebastien Bourdeauducq
3d0c3cc1cf
gateware,runtime: optimize RTIO output interface
...
* reduce address to 8 bits
* merge core, channel and address into 32-bit pre-computable "target"
* merge we register into data register
2018-11-07 23:39:58 +08:00
Sebastien Bourdeauducq
ad0254c17b
Merge branch 'switching125' into new
2018-11-07 22:03:18 +08:00
Sebastien Bourdeauducq
efd735a6ab
Revert "drtio: monitor RTIOClockMultiplier PLL ( #1155 )"
...
This reverts commit 469a66db61
.
2018-11-07 22:01:03 +08:00
Robert Jördens
ba4bf6e59b
kasli: don't pass rtio pll feedback through bufg
...
UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:58:55 +00:00
Robert Jördens
b6e4961b0f
kasli: lower RTIO clock jitter
...
* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:43:19 +00:00
Robert Jördens
e17e458c58
ptb2: add sync to urukul0 for ad9910 usage
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 10:06:51 +00:00
Robert Jördens
31f68ddf6c
Merge branch 'urukul-sync'
...
* urukul-sync: (29 commits)
urukul: flake8 [nfc]
ad9910: flake8 [nfc]
urukul/ad9910 test: remove unused import
test_urukul: relax speed
urukul,ad9910: print speed metrics
kasli: add PTB2 (external clock and SYNC)
kasli: add sync to LUH, HUB, Opticlock
kasli_tester: urukul0 mmcx clock defunct
test_ad9910: relax ifc mode read
tests: add Urukul-AD9910 HITL unittests including SYNC
ad9910: add init bit explanation
test: add Urukul CPLD HITL tests
ad9910: fiducial timestamp for tracking phase mode
ad9910: add phase modes
ad9910: fix pll timeout loop
tester: add urukul sync
ptb: back out urukul-sync
ad9910: add IO_UPDATE alignment and tuning
urukul: set up sync_in generator
ad9910: add io_update alignment measurement
...
close #1143
2018-11-05 19:54:30 +01:00
Robert Jördens
32d538f72b
kasli: add PTB2 (external clock and SYNC)
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:16 +01:00
Robert Jördens
d8a5951a13
kasli: add sync to LUH, HUB, Opticlock
...
for #1143 , also add missing LUH device db
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:14 +01:00
Robert Jördens
4269d5ad5c
tester: add urukul sync
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:52 +01:00
Robert Jördens
60d3bc63a7
ptb: back out urukul-sync
...
... for backwards compatibility.
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:50 +01:00
Robert Jördens
3538444876
urukul: add sync_in to eem0-7 name
...
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:32 +01:00
Robert Jördens
0433e8f4fe
urukul: add sync_in generator
...
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
Sebastien Bourdeauducq
bc4a8157c0
kasli: add tsinghua2
2018-11-01 18:26:37 +08:00
Sebastien Bourdeauducq
48a142ed63
use FutureWarning instead of DeprecationWarning
...
DeprecationWarning is disabled by default and too easy to ignore.
2018-10-21 12:14:51 +08:00
Sebastien Bourdeauducq
6357a50d33
kasli: update nudt variant
2018-10-15 18:04:57 +08:00
Sebastien Bourdeauducq
469a66db61
drtio: monitor RTIOClockMultiplier PLL ( #1155 )
...
Debugging by Tom Harty
2018-10-08 14:50:02 +02:00
Sebastien Bourdeauducq
86fe6b0594
kasli: add NUDT variant
2018-10-04 23:20:09 +08:00
Sebastien Bourdeauducq
a89bd6b684
kasli: swap Urukul EEMs for Tester
...
Updated to Urukul 1.3.
2018-10-04 23:19:31 +08:00
Sebastien Bourdeauducq
9f96b6bcda
kasli: use 125MHz DRTIO freq for testing
2018-10-04 10:41:01 +08:00
Sebastien Bourdeauducq
969a305c5a
Merge branch 'master' into switching125
2018-10-04 10:08:42 +08:00
Robert Jördens
d0ee2c2955
opticlock: external 100 MHz
2018-09-28 19:05:18 +02:00
Sebastien Bourdeauducq
3b3fddb5a4
kasli: add mitll2
2018-09-27 23:21:52 +08:00
Sebastien Bourdeauducq
b92350b0f6
drtio: monitor RTIOClockMultiplier PLL ( #1155 )
...
Debugging by Tom Harty
2018-09-26 10:52:08 +08:00
Sebastien Bourdeauducq
212892d92f
style
2018-09-26 10:13:33 +08:00
Sebastien Bourdeauducq
73f0de7c79
sayma: DRTIO master fixes
2018-09-20 11:15:45 +08:00
Sebastien Bourdeauducq
53a979e74d
rtio: cleanup resets
2018-09-20 10:58:38 +08:00
Sebastien Bourdeauducq
251d90c3d5
drtio: clear read request in satellite only after reply has been fully sent
...
Otherwise, chan_sel become invalid before the end of the packet, which
can cause the interconnect to invalidate i_timestamp and i_data which results
in corruption of the end of the packet.
2018-09-20 08:53:45 +08:00
Sebastien Bourdeauducq
69d060b639
drtio: fix satellite i_status handling
2018-09-19 20:57:21 +08:00
Sebastien Bourdeauducq
b86b6dcc09
drtio: add switching input test
2018-09-19 17:50:29 +08:00
Sebastien Bourdeauducq
08be176369
drtio: fix satellite i_status handling
2018-09-19 17:50:18 +08:00
Sebastien Bourdeauducq
3d965910f7
Revert "drtio: implement per-destination underflow margins"
...
This reverts commit 142c952e3d
.
2018-09-19 17:05:48 +08:00
Sebastien Bourdeauducq
142c952e3d
drtio: implement per-destination underflow margins
2018-09-19 17:03:15 +08:00
Sebastien Bourdeauducq
970d1bf147
drtio: add switching unittest
2018-09-18 15:27:52 +08:00
Sebastien Bourdeauducq
eda15a596c
drtio: add buffering to repeater
2018-09-18 15:27:25 +08:00
Sebastien Bourdeauducq
2b44786f73
drtio: add repeater input support
2018-09-17 23:45:27 +08:00
Sebastien Bourdeauducq
d38755feff
drtio: implement destination state checks on operations
2018-09-15 15:55:45 +08:00
Sebastien Bourdeauducq
cd61ee858c
kasli: fix satellite TSC instantiation
2018-09-15 14:06:54 +08:00
Sebastien Bourdeauducq
1ef39a98a7
drtio: implement per-destination buffer space
2018-09-13 16:16:32 +08:00
Sebastien Bourdeauducq
0befec7d26
drtio: improve repeater error reports
2018-09-12 20:54:01 +08:00
Sebastien Bourdeauducq
420e1cb1d0
cri: fix firmware routing table access
2018-09-12 18:08:16 +08:00
Sebastien Bourdeauducq
5bcd40ff59
cri: fix routing table depth
2018-09-12 17:30:55 +08:00
Sebastien Bourdeauducq
edf403b837
drtio: improve error reporting
2018-09-12 15:44:34 +08:00
Sebastien Bourdeauducq
95432a4ac1
drtio: remove old debugging features
2018-09-12 13:01:27 +08:00
Sebastien Bourdeauducq
41972d6773
drtio: rt_packet_satellite CRI fixes
2018-09-11 22:19:55 +08:00
Sebastien Bourdeauducq
051bafbfd9
drtio: ensure 2 cycles between frames on the link
...
This gives time for setting chan_sel before cmd on CRI.
2018-09-11 22:18:42 +08:00
Sebastien Bourdeauducq
251b9a2b0d
drtio: do not lock up master when satellite repeatedly fails to answer buffer space reqs
2018-09-11 22:17:57 +08:00
Sebastien Bourdeauducq
7ec45efdcf
kasli: add missing cri_con to Satellite
2018-09-10 20:16:09 +08:00
Sebastien Bourdeauducq
7ae44f3417
firmware: add routing table (WIP)
2018-09-09 21:49:28 +08:00
Sebastien Bourdeauducq
496d1b08fd
kasli: enable routing in Master
2018-09-09 21:48:12 +08:00
Sebastien Bourdeauducq
ec302747e0
kasli: add DRTIO repeaters
2018-09-09 16:27:39 +08:00
Sebastien Bourdeauducq
d5577ec0d0
cri: add routing table support
2018-09-09 16:26:48 +08:00
Sebastien Bourdeauducq
df61b85988
drtio: fix imports
2018-09-09 14:11:32 +08:00
Robert Jördens
312256a18d
grabber: fix frame size off-by-1
2018-09-07 16:55:43 +02:00
Sebastien Bourdeauducq
ec62eb9373
drtio: minor cleanup
2018-09-07 17:51:38 +08:00
Robert Jördens
4d73fb5bc9
grabber: only advance when DVAL
2018-09-06 11:01:08 +02:00
Sebastien Bourdeauducq
87e0384e97
drtio: separate aux controller
...
This helps with managing CSR groups and heterogeneous (satellite/repeaters) DRTIO cores.
2018-09-05 17:56:58 +08:00
Sebastien Bourdeauducq
92be9324df
add missing files
2018-09-05 16:09:02 +08:00
Sebastien Bourdeauducq
2884d595b3
drtio: add rt_controller_repeater
2018-09-05 16:08:40 +08:00
Sebastien Bourdeauducq
839f748a1d
drtio: add external TSC to repeater
2018-09-05 15:55:20 +08:00
Sebastien Bourdeauducq
5f20d79408
drtio: add timeout on satellite internal CRI buffer space request
2018-09-05 14:12:11 +08:00
Sebastien Bourdeauducq
1450e17a73
sayma: adapt to TSC and DRTIOSatellite changes
2018-09-05 12:10:41 +08:00
Sebastien Bourdeauducq
19ae9ac1b1
kc705: adapt to TSC changes
2018-09-05 12:07:28 +08:00
Sebastien Bourdeauducq
3d531cc923
kasli: adapt to TSC and DRTIOSatellite changes
2018-09-05 12:06:47 +08:00
Sebastien Bourdeauducq
4e4398afa6
analyzer: adapt to TSC changes
2018-09-05 12:06:20 +08:00
Robert Jördens
47eb37e212
VLBAI{Master,Slave}: align rtio channels with PTB
2018-09-04 10:39:45 +00:00
Sebastien Bourdeauducq
778f1de121
drtio: add TSC sync and missed command detection to rt_packet_repeater
2018-09-03 18:26:13 +08:00
hartytp
c55460f59f
suservo: fix doc typo
2018-09-03 11:48:40 +02:00
Sebastien Bourdeauducq
00fabee1ca
drtio: fix rt_packet_repeater timeout
2018-09-03 09:57:15 +08:00
Sebastien Bourdeauducq
f3fe818049
rtio: refactor TSC to allow sharing between cores
2018-09-03 09:48:12 +08:00
Sebastien Bourdeauducq
0fe2a6801e
drtio: forward destination with channel
2018-09-02 15:50:23 +08:00
Sebastien Bourdeauducq
6768dbab6c
drtio: add buffer space support to rt_packet_repeater
2018-09-02 14:38:37 +08:00
Sebastien Bourdeauducq
88b7529d09
drtio: share CDC
2018-09-02 14:37:29 +08:00
Sebastien Bourdeauducq
078c862618
drtio: add repeater (WIP, write only)
2018-09-01 21:07:55 +08:00
Sebastien Bourdeauducq
6057cb797c
drtio: reorganize tests
2018-08-31 16:28:33 +08:00
Sebastien Bourdeauducq
4f963e1e11
drtio: minor cleanup
2018-08-30 15:15:32 +08:00
Sebastien Bourdeauducq
ce6e390d5f
drtio: expose internal satellite CRI
2018-08-30 12:41:09 +08:00
Robert Jördens
e7dba34475
kasli/tester: fill all 12 EEM
2018-08-29 18:09:09 +00:00
Robert Jördens
fbf05db5ab
kasli: add VLBAI Master and Satellite
2018-08-29 17:53:48 +00:00
Robert Jördens
9584c30a1f
kasli: DRTIO Base: flexible rtio_clk_freq
2018-08-29 17:53:48 +00:00
Robert Jördens
eb9e9634df
siphaser: support 125 MHz rtio clk
...
keep the phase shift increment/decrement at 1/(56*8) rtio_clk
cycles
2018-08-29 17:53:48 +00:00
Sebastien Bourdeauducq
aa64e6c1c6
cri: add buffer space request protocol
2018-08-29 15:16:43 +08:00
Sebastien Bourdeauducq
9b6ea47b7a
kasli: use SFP LEDs to show DRTIO link status. Closes #1073
2018-08-19 13:04:41 +08:00
Sebastien Bourdeauducq
167e97efd2
sayma: support external RTM clocking
2018-08-17 22:57:54 +08:00
Sebastien Bourdeauducq
041dc0f64a
jesd204: update core to v0.10
...
Closes #727
Closes #1127
2018-08-17 22:50:07 +08:00
Sebastien Bourdeauducq
49f7a1610f
sayma: use GTP_CLK1 only for all variants ( #1080 )
2018-08-07 20:53:14 +08:00
Sebastien Bourdeauducq
e2a49ce368
drtio: support external IBUFDS_GTE3
2018-08-07 20:52:45 +08:00
Sebastien Bourdeauducq
9ce6233926
kasli: fix SYSU TTL directions
2018-08-07 19:29:28 +08:00
Sebastien Bourdeauducq
65f198bdee
kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example
2018-08-06 16:53:13 +08:00
Sebastien Bourdeauducq
b023865b42
sayma: instantiate dummy IBUFDS_GTE3 on unused but driven Si5324 clock pins
...
Solve same problem as e83ee3a0
but channels cannot be independently disabled.
2018-08-05 23:02:41 +08:00
Sebastien Bourdeauducq
e83ee3a07a
hmc7043: disable GTP_CLK1 when not in use
...
Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
2018-08-03 10:03:52 +08:00
Sebastien Bourdeauducq
b38c685857
grabber: fix pix.stb
2018-07-24 11:32:32 +08:00
Sebastien Bourdeauducq
60a7e0e40d
grabber: use usual order of ROI coordinates in cfg addresses
2018-07-24 10:55:13 +08:00
Sebastien Bourdeauducq
7b75026391
grabber: add MultiReg to transfer ROI boundaries
2018-07-21 13:40:12 +08:00
Sebastien Bourdeauducq
4a4d0f8e51
grabber: fix missing variable rename
2018-07-21 13:39:46 +08:00
Sebastien Bourdeauducq
3638a966e1
kasli: add false path between RTIO and CL clocks
2018-07-21 13:26:13 +08:00
Sebastien Bourdeauducq
031de58d21
grabber: complete RTIO PHY, untested
2018-07-21 13:25:47 +08:00
Sebastien Bourdeauducq
e3ba4b9516
grabber: minor ROI engine cleanup, export count_len, cap count width to 31
2018-07-21 13:25:13 +08:00
Sebastien Bourdeauducq
25170a53e5
sayma: add back Urukul and Zotino
2018-07-18 10:27:54 +08:00
Sebastien Bourdeauducq
7fe76426fe
fmcdio_vhdci_eem: commit missing part of previous commit
2018-07-17 20:30:13 +08:00
Sebastien Bourdeauducq
4fdc20bb11
sayma: disable Urukul and Zotino for now
...
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
2018-07-17 20:08:21 +08:00
Sebastien Bourdeauducq
8335085fd6
fmcdio_vhdci_eem: fix cc pins
2018-07-17 19:50:34 +08:00
Sebastien Bourdeauducq
8f7c0c1646
fmcdio_vhdci_eem: fix iostandard
2018-07-17 19:40:34 +08:00
Sebastien Bourdeauducq
d724bd980c
sayma: add EEMs to Master
2018-07-17 18:58:23 +08:00
Sebastien Bourdeauducq
a0f2d8c2ea
gateware: add FMCDIO/EEM adapter definitions
2018-07-17 18:58:16 +08:00
Sebastien Bourdeauducq
3645a6424e
sayma: fix Master build
2018-07-17 18:56:33 +08:00
Sebastien Bourdeauducq
9b016dcd6d
eem: support specifying I/O standard
...
Xilinx FPGAs require different LVDS I/O standard names depending on I/O bank voltage.
2018-07-17 18:55:17 +08:00