mirror of https://github.com/m-labs/artiq.git
sayma: prepare for SYSREF align
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
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@ -155,8 +155,8 @@ pub mod hmc7043 {
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(true, SYSREF_DIV, 0x08, true), // 1: DAC1_SYSREF
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(true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK
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(true, SYSREF_DIV, 0x08, true), // 3: DAC0_SYSREF
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(false, 0, 0x10, true), // 4: AMC_FPGA_SYSREF0
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(true, SYSREF_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
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(true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0
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(true, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
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(false, 0, 0x10, false), // 6: unused
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(true, SYSREF_DIV, 0x10, true), // 7: RTM_FPGA_SYSREF0
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(true, FPGA_CLK_DIV, 0x08, false), // 8: GTP_CLK0_IN
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@ -1,100 +1,123 @@
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use board_misoc::{csr, clock};
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use board_artiq::drtioaux;
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pub mod jesd {
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use board_misoc::{csr, clock};
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use super::jdac_requests;
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pub fn jesd_reset(reset: bool) {
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unsafe {
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csr::jesd_crg::jreset_write(if reset {1} else {0});
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pub fn reset(reset: bool) {
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unsafe {
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csr::jesd_crg::jreset_write(if reset {1} else {0});
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}
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}
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}
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fn jesd_enable(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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}
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fn jesd_ready(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
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}
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}
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fn jesd_prbs(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
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}
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clock::spin_us(5000);
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}
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fn jesd_stpl(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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}
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fn jesd_jsync(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
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}
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}
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fn jdac_basic_request(dacno: u8, reqno: u8) {
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
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destination: 0,
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dacno: dacno,
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reqno: reqno
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}) {
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error!("aux packet error ({})", e);
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}
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match drtioaux::recv_timeout(1, Some(1000)) {
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Ok(drtioaux::Packet::JdacBasicReply { succeeded }) =>
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if !succeeded {
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error!("JESD DAC basic request failed (dacno={}, reqno={})", dacno, reqno);
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},
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Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
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Err(e) => error!("aux packet error ({})", e),
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}
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}
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pub fn init() {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("DAC-{} initializing...", dacno);
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jesd_enable(dacno, true);
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jesd_prbs(dacno, false);
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jesd_stpl(dacno, false);
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jdac_basic_request(dacno, jdac_requests::INIT);
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jesd_prbs(dacno, true);
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jdac_basic_request(dacno, jdac_requests::PRBS);
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jesd_prbs(dacno, false);
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jesd_stpl(dacno, true);
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jdac_basic_request(dacno, jdac_requests::STPL);
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jesd_stpl(dacno, false);
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jdac_basic_request(dacno, jdac_requests::INIT);
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let t = clock::get_ms();
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while !jesd_ready(dacno) {
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if clock::get_ms() > t + 200 {
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error!("JESD ready timeout");
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break;
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}
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pub fn enable(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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jdac_basic_request(dacno, jdac_requests::PRINT_STATUS);
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}
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if !jesd_jsync(dacno) {
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error!("bad SYNC");
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pub fn ready(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_ready_read)() != 0
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}
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}
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info!(" ...done");
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pub fn prbs(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_prbs_config_write)(if en {0b01} else {0b00})
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}
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clock::spin_us(5000);
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}
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pub fn stpl(dacno: u8, en: bool) {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_stpl_enable_write)(if en {1} else {0})
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}
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clock::spin_us(5000);
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}
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pub fn jsync(dacno: u8) -> bool {
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unsafe {
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(csr::JDCG[dacno as usize].jesd_control_jsync_read)() != 0
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}
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}
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}
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pub mod jdac {
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use board_misoc::{csr, clock};
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use board_artiq::drtioaux;
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use super::jesd;
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use super::super::jdac_requests;
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pub fn basic_request(dacno: u8, reqno: u8) {
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
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destination: 0,
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dacno: dacno,
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reqno: reqno
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}) {
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error!("aux packet error ({})", e);
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}
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match drtioaux::recv_timeout(1, Some(1000)) {
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Ok(drtioaux::Packet::JdacBasicReply { succeeded }) =>
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if !succeeded {
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error!("JESD DAC basic request failed (dacno={}, reqno={})", dacno, reqno);
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},
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Ok(packet) => error!("received unexpected aux packet: {:?}", packet),
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Err(e) => error!("aux packet error ({})", e),
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}
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}
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pub fn init() {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("DAC-{} initializing...", dacno);
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jesd::enable(dacno, true);
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clock::spin_us(10);
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if !jesd::ready(dacno) {
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error!("JESD core reported not ready");
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}
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basic_request(dacno, jdac_requests::INIT);
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jesd::prbs(dacno, true);
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basic_request(dacno, jdac_requests::PRBS);
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jesd::prbs(dacno, false);
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jesd::stpl(dacno, true);
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basic_request(dacno, jdac_requests::STPL);
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jesd::stpl(dacno, false);
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basic_request(dacno, jdac_requests::INIT);
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clock::spin_us(5000);
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basic_request(dacno, jdac_requests::PRINT_STATUS);
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if !jesd::jsync(dacno) {
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error!("JESD core reported bad SYNC");
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}
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info!(" ...done");
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}
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}
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}
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pub mod jesd204sync {
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fn sysref_auto_rtio_align() -> Result<(), &'static str> {
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info!("TODO: sysref_auto_rtio_align");
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Ok(())
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}
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fn sysref_auto_dac_align() -> Result<(), &'static str> {
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info!("TODO: sysref_auto_dac_align");
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Ok(())
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}
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pub fn sysref_auto_align() {
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if let Err(e) = sysref_auto_rtio_align() {
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error!("failed to align SYSREF at FPGA: {}", e);
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}
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if let Err(e) = sysref_auto_dac_align() {
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error!("failed to align SYSREF at DAC: {}", e);
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}
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}
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}
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@ -498,9 +498,9 @@ pub extern fn main() -> i32 {
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* To handle those cases, we simply keep the JESD204 core in reset unless the
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* Si5324 is locked to the recovered clock.
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*/
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jdcg::jesd_reset(false);
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jdcg::jesd::reset(false);
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if repeaters[0].is_up() {
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jdcg::init();
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jdcg::jdac::init();
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}
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}
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@ -516,26 +516,15 @@ pub extern fn main() -> i32 {
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for mut rep in repeaters.iter_mut() {
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rep.service(&routing_table, rank);
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}
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#[cfg(has_jdcg)]
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{
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let rep0_is_up = repeaters[0].is_up();
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if rep0_is_up && !rep0_was_up {
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jdcg::init();
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}
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rep0_was_up = rep0_is_up;
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}
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hardware_tick(&mut hardware_tick_ts);
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if drtiosat_tsc_loaded() {
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info!("TSC loaded from uplink");
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/* TODO: #[cfg(has_jdcg)]
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#[cfg(has_jdcg)]
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{
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align() {
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error!("failed to align SYSREF at FPGA: {}", e);
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if rep0_was_up {
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jdcg::jesd204sync::sysref_auto_align();
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}
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if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
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error!("failed to align SYSREF at DAC: {}", e);
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}
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} */
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}
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for rep in repeaters.iter() {
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if let Err(e) = rep.sync_tsc() {
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error!("failed to sync TSC ({})", e);
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error!("aux packet error: {}", e);
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}
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}
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#[cfg(has_jdcg)]
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{
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let rep0_is_up = repeaters[0].is_up();
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if rep0_is_up && !rep0_was_up {
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jdcg::jdac::init();
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jdcg::jesd204sync::sysref_auto_align();
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}
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rep0_was_up = rep0_is_up;
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}
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}
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#[cfg(has_jdcg)]
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jdcg::jesd_reset(true);
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jdcg::jesd::reset(true);
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drtiosat_reset_phy(true);
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drtiosat_reset(true);
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@ -58,6 +58,7 @@ class SatelliteBase(BaseSoC):
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l2_size=128*1024,
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**kwargs)
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add_identifier(self, suffix=identifier_suffix)
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self.rtio_clk_freq = rtio_clk_freq
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platform = self.platform
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@ -279,11 +280,17 @@ class Satellite(SatelliteBase):
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self.add_rtio(rtio_channels)
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
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platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts)
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self.csr_devices.append("sysref_sampler")
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self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
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self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
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# DDMTD
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# https://github.com/sinara-hw/Sayma_RTM/issues/68
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sysref_pads = platform.request("amc_fpga_sysref", 1)
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
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self.csr_devices.append("sysref_ddmtd")
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class SimpleSatellite(SatelliteBase):
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def __init__(self, **kwargs):
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@ -21,7 +21,6 @@ from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.gateware import jesd204_tools
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from artiq.build_soc import add_identifier
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from artiq import __artiq_dir__ as artiq_dir
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@ -216,12 +215,6 @@ class Satellite(_SatelliteBase):
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platform.request("hmc7043_out_en"))
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self.csr_devices.append("hmc7043_out_en")
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# DDMTD
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# https://github.com/sinara-hw/Sayma_RTM/issues/68
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sysref_pads = platform.request("rtm_fpga_sysref", 1) # use odd-numbered 7043 output
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self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
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self.csr_devices.append("sysref_ddmtd")
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class SatmanSoCBuilder(Builder):
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def __init__(self, *args, **kwargs):
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