mirror of https://github.com/m-labs/artiq.git
sayma_rtm2: si5324_clkout -> cdr_clk_clean
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@ -195,7 +195,7 @@ class SaymaRTM(Module):
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sysref_pads = platform.request("rtm_master_aux_clk")
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elif hw_rev == "v2.0":
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# https://github.com/sinara-hw/Sayma_RTM/issues/68
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rtio_clock_pads = platform.request("si5324_clkout_fabric")
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rtio_clock_pads = platform.request("cdr_clk_clean_fabric")
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sysref_pads = platform.request("rtm_fpga_sysref", 1) # use odd-numbered 7043 output
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else:
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raise NotImplementedError
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@ -82,7 +82,7 @@ class _SatelliteBase(BaseSoC):
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = platform.request("si5324_clkout")
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si5324_clkout = platform.request("cdr_clk_clean")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=disable_si5324_ibuf,
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