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sayma_rtm2: select filtered clock from Si5324

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Sebastien Bourdeauducq 2019-10-04 22:56:16 +08:00
parent 6cb0f5de59
commit 6aa68e1715
1 changed files with 2 additions and 0 deletions
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artiq/gateware/targets/sayma_rtm_drtio.py
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@ -136,6 +136,8 @@ class _SatelliteBase(BaseSoC):
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if self.hw_rev == "v2.0":
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,