M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

sayma_amc: remove dummy FPGA pin assignment testing code

pull/1371/head
Sebastien Bourdeauducq 2019-10-05 09:24:44 +08:00
parent ada3b39f4e
commit 96fc4a21e8
1 changed files with 0 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/gateware/targets/sayma_amc.py
View File

@ -444,17 +444,6 @@ class Satellite(BaseSoC, RTMCommon):
self.crg.cd_sys.clk,
gth.txoutclk, gth.rxoutclk)
# placeholder code to test I/O routing and standards
if self.hw_rev == "v2.0":
self.clock_domains.cd_ddmtd_helper = ClockDomain(reset_less=True)
helper_clk = platform.request("ddmtd_helper_clk")
self.specials += Instance("IBUFGDS",
i_I=helper_clk.p, i_IB=helper_clk.n,
o_O=self.cd_ddmtd_helper.clk)
ddmtd = platform.request("ddmtd_results")
self.sync.ddmtd_helper += platform.request("tp16").eq(
ddmtd.rec_clk ^ ddmtd.main_xo)
def main():
parser = argparse.ArgumentParser(