mirror of https://github.com/m-labs/artiq.git
wrpll/thls: support processor start/stop
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623446f82c
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@ -5,6 +5,7 @@ import operator
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from functools import reduce
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from migen import *
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from migen.genlib.fsm import *
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class Isn:
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@ -53,6 +54,9 @@ class InputIsn(Isn):
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class OutputIsn(Isn):
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opcode = 6
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class EndIsn(Isn):
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opcode = 7
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class ASTCompiler:
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def __init__(self):
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@ -298,11 +302,14 @@ def compile(processor, function):
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scheduler = Scheduler(processor, len(astcompiler.data), astcompiler.program)
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scheduler.schedule()
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max_reg = max(max(max(isn.inputs + [0]) for isn in scheduler.output), max(v[1] for k, v in scheduler.exits.items()))
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program = copy(scheduler.output)
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program.append(EndIsn())
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max_reg = max(max(max(isn.inputs + [0]) for isn in program), max(v[1] for k, v in scheduler.exits.items()))
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return CompiledProgram(
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processor=processor,
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program=scheduler.output,
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program=program,
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exits={k: v[1] for k, v in scheduler.exits.items()},
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data=astcompiler.data + [0]*(max_reg - len(astcompiler.data) + 1),
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glbs=astcompiler.globals)
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@ -355,11 +362,11 @@ class CopyUnit(BaseUnit):
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class InputUnit(BaseUnit):
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def __init__(self, data_width, input_stb, input):
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BaseUnit.__init__(self, data_width)
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self.buffer = Signal(data_width)
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# TODO
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self.comb += [
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self.stb_o.eq(self.stb_i),
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self.o.eq(42)
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self.o.eq(self.buffer)
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]
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@ -381,6 +388,8 @@ class ProcessorImpl(Module):
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self.output_stb = Signal()
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self.output = Signal(pd.data_width)
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self.busy = Signal()
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# # #
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program_mem = Memory(pd.instruction_bits(), pd.program_rom_size, init=program)
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@ -403,9 +412,6 @@ class ProcessorImpl(Module):
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self.specials += program_mem_port
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self.comb += program_mem_port.adr.eq(pc_next)
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# TODO
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self.comb += pc_en.eq(1)
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s = 0
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opcode = Signal(pd.opcode_bits)
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self.comb += opcode.eq(program_mem_port.dat_r[s:s+pd.opcode_bits])
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@ -448,7 +454,7 @@ class ProcessorImpl(Module):
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self.submodules += units
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for n, unit in enumerate(units):
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self.sync += unit.stb_i.eq(opcode == n)
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self.sync += unit.stb_i.eq(pc_en & (opcode == n))
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self.comb += [
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unit.i0.eq(data_read_port0.dat_r),
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unit.i1.eq(data_read_port1.dat_r),
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@ -458,6 +464,22 @@ class ProcessorImpl(Module):
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)
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]
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fsm = FSM()
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self.submodules += fsm
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fsm.act("IDLE",
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pc_en.eq(0),
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NextValue(inu.buffer, self.input),
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If(self.input_stb, NextState("PROCESSING"))
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)
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fsm.act("PROCESSING",
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self.busy.eq(1),
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pc_en.eq(1),
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If(opcode == EndIsn.opcode,
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pc_en.eq(0),
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NextState("IDLE")
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)
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)
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a = 0
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b = 0
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@ -472,8 +494,7 @@ def foo(x):
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def simple_test(x):
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a = 5 + 3
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return a*4
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return x*2+2
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if __name__ == "__main__":
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@ -484,9 +505,22 @@ if __name__ == "__main__":
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print(cp.encode())
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proc_impl = proc.implement(cp.encode(), cp.data)
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def wait_result():
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while not (yield proc_impl.output_stb):
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def send_values(values):
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for value in values:
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yield proc_impl.input.eq(value)
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yield proc_impl.input_stb.eq(1)
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yield
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result = yield proc_impl.output
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print(result)
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run_simulation(proc_impl, [wait_result()], vcd_name="test.vcd")
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yield proc_impl.input.eq(0)
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yield proc_impl.input_stb.eq(0)
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yield
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while (yield proc_impl.busy):
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yield
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@passive
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def receive_values(callback):
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while True:
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while not (yield proc_impl.output_stb):
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yield
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callback((yield proc_impl.output))
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yield
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run_simulation(proc_impl, [send_values([42, 40]), receive_values(print)])
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