mirror of https://github.com/m-labs/artiq.git
sayma_amc: refactor, add SimpleSatellite variant
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58b7bdcecc
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7b95814cf5
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@ -25,6 +25,144 @@ from artiq.gateware.drtio import *
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from artiq.build_soc import *
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
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# timing analysis. Disable the latter for IOBUFDS.
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# See:
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# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
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platform.add_platform_command(
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"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
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class RTMUARTForward(Module):
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def __init__(self, platform):
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# forward RTM UART to second FTDI UART channel
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serial_1 = platform.request("serial", 1)
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serial_rtm = platform.request("serial_rtm")
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self.comb += [
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serial_1.tx.eq(serial_rtm.rx),
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serial_rtm.tx.eq(serial_1.rx)
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]
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class SatelliteBase(BaseSoC):
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mem_map = {
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"drtioaux": 0x14000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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**kwargs)
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add_identifier(self, suffix=identifier_suffix)
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platform = self.platform
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# Use SFP0 to connect to master (Kasli)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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drtio_data_pads = [platform.request("sfp", 0)]
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if self.hw_rev == "v2.0":
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drtio_data_pads.append(platform.request("rtm_amc_link"))
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean"),
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[i],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if self.hw_rev == "v2.0":
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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def add_rtio(self, rtio_channels):
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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class AD9154(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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@ -77,16 +215,6 @@ class AD9154NoSAWG(Module, AutoCSR):
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Cat(samples[3]).eq(Cat(samples[1]))
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]
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class RTMUARTForward(Module):
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def __init__(self, platform):
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# forward RTM UART to second FTDI UART channel
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serial_1 = platform.request("serial", 1)
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serial_rtm = platform.request("serial_rtm")
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self.comb += [
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serial_1.tx.eq(serial_rtm.rx),
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serial_rtm.tx.eq(serial_1.rx)
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]
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class RTMSerWb:
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def __init__(self):
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@ -115,14 +243,95 @@ class RTMSerWb:
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
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# timing analysis. Disable the latter for IOBUFDS.
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# See:
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# https://forums.xilinx.com/t5/Timing-Analysis/Delay-890-ns-in-OBUFTDS-in-Kintex-UltraScale/td-p/868364
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platform.add_platform_command(
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"set_false_path -through [get_pins -filter {{REF_PIN_NAME == T}} -of [get_cells -filter {{REF_NAME == IOBUFDS}}]]")
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class Satellite(SatelliteBase, RTMSerWb):
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"""
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DRTIO satellite with local DAC/SAWG channels.
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"""
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mem_map = {
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"serwb": 0x13000000,
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}
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mem_map.update(SatelliteBase.mem_map)
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def __init__(self, with_sawg, **kwargs):
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SatelliteBase.__init__(self, 150e6,
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identifier_suffix=".without-sawg" if not with_sawg else "",
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**kwargs)
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RTMSerWb.__init__(self)
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platform = self.platform
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self.submodules += RTMUARTForward(platform)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HMC830_REF"] = "150"
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(
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platform, use_rtio_clock=True)
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_crg")
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs +
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self.ad9154_1.sawgs
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for phy in sawg.phys)
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self.add_rtio(rtio_channels)
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
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self.csr_devices.append("sysref_sampler")
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self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
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self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
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class SimpleSatellite(SatelliteBase):
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def __init__(self, **kwargs):
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SatelliteBase.__init__(self, **kwargs)
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platform = self.platform
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self.submodules += RTMUARTForward(platform)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(rtio_channels)
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class Master(MiniSoC, AMPSoC):
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@ -279,170 +488,6 @@ class Master(MiniSoC, AMPSoC):
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self.csr_devices.append("routing_table")
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class Satellite(BaseSoC, RTMSerWb):
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"""
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DRTIO satellite with local DAC/SAWG channels.
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Use SFP0 to connect to master (Kasli/Sayma).
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"""
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mem_map = {
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"serwb": 0x13000000,
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"drtioaux": 0x14000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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**kwargs)
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RTMSerWb.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "150"
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += RTMUARTForward(platform)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(
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platform, use_rtio_clock=True)
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_crg")
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs +
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self.ad9154_1.sawgs
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for phy in sawg.phys)
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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drtio_data_pads = [platform.request("sfp", 0)]
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if self.hw_rev == "v2.0":
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drtio_data_pads.append(platform.request("rtm_amc_link"))
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean"),
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[i],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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||||
self.add_wb_slave(memory_address, 0x800,
|
||||
coreaux.bus)
|
||||
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.config["HAS_DRTIO_ROUTING"] = None
|
||||
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
||||
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
||||
self.add_csr_group("drtiorep", drtiorep_csr_group)
|
||||
|
||||
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
||||
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.drtiosat.cri],
|
||||
[self.local_io.cri] + drtio_cri,
|
||||
mode="sync", enable_routing=True)
|
||||
self.csr_devices.append("cri_con")
|
||||
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
||||
self.csr_devices.append("routing_table")
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
||||
if self.hw_rev == "v2.0":
|
||||
self.comb += platform.request("filtered_clk_sel").eq(1)
|
||||
self.submodules.siphaser = SiPhaser7Series(
|
||||
si5324_clkin=platform.request("si5324_clkin"),
|
||||
rx_synchronizer=self.rx_synchronizer,
|
||||
ultrascale=True,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
|
||||
self.csr_devices.append("siphaser")
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
|
||||
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
|
||||
platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
|
||||
self.csr_devices.append("sysref_sampler")
|
||||
self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
|
||||
self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
|
||||
|
||||
rtio_clk_period = 1e9/rtio_clk_freq
|
||||
gth = self.drtio_transceiver.gths[0]
|
||||
platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
|
||||
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
gth.txoutclk, gth.rxoutclk)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="Sayma AMC gateware and firmware builder")
|
||||
|
|
@ -450,7 +495,7 @@ def main():
|
|||
soc_sayma_amc_args(parser)
|
||||
parser.set_defaults(output_dir="artiq_sayma")
|
||||
parser.add_argument("-V", "--variant", default="satellite",
|
||||
help="variant: master/satellite "
|
||||
help="variant: satellite/simplesatellite/master "
|
||||
"(default: %(default)s)")
|
||||
parser.add_argument("--rtm-csr-csv",
|
||||
default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
|
||||
|
|
@ -462,15 +507,8 @@ def main():
|
|||
args = parser.parse_args()
|
||||
|
||||
variant = args.variant.lower()
|
||||
if variant == "master":
|
||||
cls = lambda with_sawg, **kwargs: Master(**kwargs)
|
||||
elif variant == "satellite":
|
||||
cls = Satellite
|
||||
else:
|
||||
raise SystemExit("Invalid variant (-V/--variant)")
|
||||
soc = cls(with_sawg=not args.without_sawg, **soc_sayma_amc_argdict(args))
|
||||
|
||||
if variant != "master":
|
||||
if variant == "satellite":
|
||||
soc = Satellite(with_sawg=not args.without_sawg, **soc_sayma_amc_argdict(args))
|
||||
remote_csr_regions = remote_csr.get_remote_csr_regions(
|
||||
soc.mem_map["serwb"] | soc.shadow_base,
|
||||
args.rtm_csr_csv)
|
||||
|
|
@ -481,6 +519,12 @@ def main():
|
|||
soc.config["CONVERTER_SPI_HMC830_CS"] = 0
|
||||
soc.config["CONVERTER_SPI_HMC7043_CS"] = 1
|
||||
soc.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
|
||||
elif variant == "simplesatellite":
|
||||
soc = SimpleSatellite(**soc_sayma_amc_argdict(args))
|
||||
elif variant == "master":
|
||||
soc = Master(**soc_sayma_amc_argdict(args))
|
||||
else:
|
||||
raise SystemExit("Invalid variant (-V/--variant)")
|
||||
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue