mirror of https://github.com/m-labs/artiq.git
sayma_amc: do not use SFP0 (now used for Ethernet)
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@ -162,13 +162,10 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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self.csr_devices.append("ad9154_crg")
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self.comb += [
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platform.request("sfp_tx_disable", i).eq(0)
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for i in range(2)
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]
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self.comb += platform.request("sfp_tx_disable", 1).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=self.ad9154_crg.refclk,
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data_pads=[platform.request("sata")] + [platform.request("sfp", i) for i in range(2)],
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data_pads=[platform.request("sata"), platform.request("sfp", 1)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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@ -179,7 +176,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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for i in range(3):
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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@ -346,14 +343,12 @@ class Master(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += [
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platform.request("sfp_tx_disable", i).eq(0)
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for i in range(2)
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]
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self.comb += platform.request("sfp_tx_disable", 1).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean", 0),
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data_pads=[platform.request("sfp", i) for i in range(2)] +
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[platform.request("rtm_gth", i) for i in range(8)],
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data_pads=[platform.request("sfp", 1)] +
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# 6 and not 8 to work around Vivado bug (Xilinx CR 1020646)
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[platform.request("rtm_gth", i) for i in range(6)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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@ -364,7 +359,7 @@ class Master(MiniSoC, AMPSoC):
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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for i in range(10):
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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