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https://github.com/m-labs/artiq.git
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wrpll: add I2CMasterMachine
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parent
1fd2322662
commit
959679d8b7
@ -5,6 +5,148 @@ from migen.genlib.cdc import MultiReg, PulseSynchronizer, BlindTransfer
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from misoc.interconnect.csr import *
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class I2CClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.clk2x = Signal()
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cnt = Signal.like(self.load)
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self.comb += [
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self.clk2x.eq(cnt == 0),
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]
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self.sync += [
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If(self.clk2x,
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cnt.eq(self.load),
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).Else(
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cnt.eq(cnt - 1),
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)
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]
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class I2CMasterMachine(Module):
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def __init__(self, clock_width):
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self.scl = Signal(reset=1)
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self.sda_o = Signal(reset=1)
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self.sda_i = Signal()
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self.submodules.cg = CEInserter()(I2CClockGen(clock_width))
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self.idle = Signal()
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self.start = Signal()
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self.stop = Signal()
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self.write = Signal()
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self.read = Signal()
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self.ack = Signal()
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self.data = Signal(8)
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###
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busy = Signal()
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bits = Signal(4)
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.start,
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NextState("START0"),
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).Elif(self.stop & self.start,
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NextState("RESTART0"),
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).Elif(self.stop,
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NextState("STOP0"),
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).Elif(self.write,
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NextValue(bits, 8),
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NextState("WRITE0"),
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).Elif(self.read,
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NextValue(bits, 8),
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NextState("READ0"),
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)
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)
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fsm.act("START0",
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NextValue(self.scl, 1),
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NextState("START1"))
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fsm.act("START1",
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NextValue(self.sda_o, 0),
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NextState("IDLE"))
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fsm.act("RESTART0",
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NextValue(self.scl, 0),
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NextState("RESTART1"))
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fsm.act("RESTART1",
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NextValue(self.sda_o, 1),
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NextState("START0"))
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fsm.act("STOP0",
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NextValue(self.scl, 0),
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NextState("STOP1"))
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fsm.act("STOP1",
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NextValue(self.scl, 1),
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NextValue(self.sda_o, 0),
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NextState("STOP2"))
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fsm.act("STOP2",
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NextValue(self.sda_o, 1),
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NextState("IDLE"))
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fsm.act("WRITE0",
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NextValue(self.scl, 0),
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If(bits == 0,
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NextValue(self.sda_o, 1),
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NextState("READACK0"),
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).Else(
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NextValue(self.sda_o, self.data[7]),
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NextState("WRITE1"),
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)
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)
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fsm.act("WRITE1",
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NextValue(self.scl, 1),
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NextValue(self.data[1:], self.data[:-1]),
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NextValue(bits, bits - 1),
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NextState("WRITE0"),
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)
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fsm.act("READACK0",
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NextValue(self.scl, 1),
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NextState("READACK1"),
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)
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fsm.act("READACK1",
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NextValue(self.ack, ~self.sda_i),
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NextState("IDLE")
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)
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fsm.act("READ0",
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NextValue(self.scl, 0),
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NextState("READ1"),
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)
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fsm.act("READ1",
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NextValue(self.data[0], self.sda_i),
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NextValue(self.scl, 0),
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If(bits == 0,
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NextValue(self.sda_o, ~self.ack),
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NextState("WRITEACK0"),
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).Else(
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NextValue(self.sda_o, 1),
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NextState("READ2"),
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)
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)
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fsm.act("READ2",
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NextValue(self.scl, 1),
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NextValue(self.data[:-1], self.data[1:]),
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NextValue(bits, bits - 1),
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NextState("READ1"),
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)
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fsm.act("WRITEACK0",
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NextValue(self.scl, 1),
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NextState("IDLE"),
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)
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run = Signal()
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self.comb += [
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run.eq(self.start | self.stop | self.write | self.read),
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self.idle.eq(~run & fsm.ongoing("IDLE")),
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self.cg.ce.eq(~self.idle),
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fsm.ce.eq(run | self.cg.clk2x),
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]
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class ADPLLProgrammer(Module):
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def __init__(self):
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self.i2c_divider = Signal(16)
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@ -18,11 +160,21 @@ class ADPLLProgrammer(Module):
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self.scl = Signal()
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self.sda_i = Signal()
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self.sda_o = Signal()
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self.sda_oe = Signal()
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self.scl.attr.add("no_retiming")
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self.sda_o.attr.add("no_retiming")
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self.sda_oe.attr.add("no_retiming")
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# # #
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master = I2CMasterMachine(16)
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self.submodules += master
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self.comb += [
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master.cg.load.eq(self.i2c_divider.storage),
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self.scl.eq(master.scl),
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master.sda_i.eq(self.sda_i),
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self.sda_o.eq(master.sda_o)
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]
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class Si549(Module, AutoCSR):
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@ -56,6 +208,10 @@ class Si549(Module, AutoCSR):
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programmer.adpll_stb.eq(self.adpll_stb)
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]
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self.gpio_enable.storage.attr.add("no_retiming")
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self.gpio_out.storage.attr.add("no_retiming")
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self.gpio_oe.storage.attr.add("no_retiming")
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# SCL GPIO and mux
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ts_scl = TSTriple(1)
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self.specials += ts_scl.get_tristate(pads.scl)
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@ -64,7 +220,6 @@ class Si549(Module, AutoCSR):
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self.comb += self.gpio_in.status[0].eq(status)
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self.specials += MultiReg(ts_scl.i, status)
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self.gpio_enable.storage.attr.add("no_retiming")
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self.comb += [
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If(self.gpio_enable.storage,
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ts_scl.o.eq(self.gpio_out.storage[0]),
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@ -83,14 +238,13 @@ class Si549(Module, AutoCSR):
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self.comb += self.gpio_in.status[1].eq(status)
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self.specials += MultiReg(ts_sda.i, status)
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self.gpio_enable.storage.attr.add("no_retiming")
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self.comb += [
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If(self.gpio_enable.storage,
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ts_sda.o.eq(self.gpio_out.storage[1]),
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ts_sda.oe.eq(self.gpio_oe.storage[1])
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).Else(
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ts_sda.o.eq(programmer.sda_o),
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ts_sda.oe.eq(programmer.sda_oe)
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ts_sda.o.eq(0),
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ts_sda.oe.eq(~programmer.sda_o)
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)
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]
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self.specials += MultiReg(ts_sda.i, programmer.sda_i, "helper")
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