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sayma_amc: sma -> mcx
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ebd5d890f1
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@ -246,14 +246,14 @@ class Satellite(SatelliteBase):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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mcx_io = platform.request("mcx_io", 0)
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self.comb += mcx_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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mcx_io = platform.request("mcx_io", 1)
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self.comb += mcx_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -298,14 +298,14 @@ class SimpleSatellite(SatelliteBase):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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mcx_io = platform.request("mcx_io", 0)
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self.comb += mcx_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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mcx_io = platform.request("mcx_io", 1)
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self.comb += mcx_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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@ -416,14 +416,14 @@ class Master(MiniSoC, AMPSoC):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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mcx_io = platform.request("mcx_io", 0)
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self.comb += mcx_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, mcx_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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mcx_io = platform.request("mcx_io", 1)
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self.comb += mcx_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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