mirror of https://github.com/m-labs/artiq.git
kasli: remove PTB/PTB2/LUH/HUB variants
see sinara-systems and nix-scripts repos
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parent
1d2cc60e0d
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0c9b810501
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@ -239,192 +239,6 @@ class SUServo(StandaloneBase):
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pads.clkout, self.crg.cd_sys.clk)
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class PTB(StandaloneBase):
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"""PTB Kasli variant
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F.k.a. ptb-schmidt, ptb-mehlstaeubler, ptb-huntemann-11, ptb-huntemann-19,
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and ufr-warring in the artiq-setup repository
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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class PTB2(StandaloneBase):
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"""PTB Kasli variant with Urukul1 SYNC and external reference clock"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["SI5324_EXT_REF"] = None
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self.config["EXT_REF_FREQUENCY"] = "100.0"
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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class HUB(StandaloneBase):
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"""HUB Kasli variant
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F.k.a. hub-krutzik, luh-ospelkaus-13, and luh-ospelkaus-14
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in the artiq-setup repository
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 4, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.Urukul.add_std(self, 5, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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class LUH(StandaloneBase):
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"""LUH Kasli variant
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F.k.a. luh-ospelkaus-16, luh-ospelkaus-18 in the artiq-setup repository
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v1.1"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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self.grabber_csr_group = []
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 4, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.Urukul.add_std(self, 5, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.Grabber.add_std(self, 6)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
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class Tester(StandaloneBase):
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"""
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Configuration for CI tests. Contains the maximum number of different EEMs.
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@ -909,7 +723,7 @@ class VLBAISatellite(SatelliteBase):
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VARIANTS = {cls.__name__.lower(): cls for cls in [
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Opticlock, SUServo, PTB, PTB2, HUB, LUH,
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Opticlock, SUServo,
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VLBAIMaster, VLBAISatellite,
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Tester, Master, Satellite]}
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