mirror of https://github.com/m-labs/artiq.git
sayma: use SFP0 for DRTIO master
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@ -361,10 +361,10 @@ class Master(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("sfp_tx_disable", 1).eq(0)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean", 0),
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data_pads=[platform.request("sfp", 1)] +
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data_pads=[platform.request("sfp", 0)] +
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# 6 and not 8 to work around Vivado bug (Xilinx CR 1020646)
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[platform.request("rtm_gth", i) for i in range(6)],
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sys_clk_freq=self.clk_freq,
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