mirror of https://github.com/m-labs/artiq.git
sayma: drop MasterDAC
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties. Now Sayma works fine with Kasli as a master, which is simpler.
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parent
b04e15741b
commit
43e58c939c
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@ -421,14 +421,6 @@ pub mod hmc7043 {
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}
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pub fn init() -> Result<(), &'static str> {
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// used by MasterDAC - HMC830 is clocked from 100MHz reference
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#[cfg(all(hmc830_ref = "100", rtio_frequency = "125.0"))]
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const DIV: (u32, u32, u32, u32) = (1, 20, 0, 1); // 100MHz -> 2.0GHz
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#[cfg(all(hmc830_ref = "100", rtio_frequency = "150.0"))]
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const DIV: (u32, u32, u32, u32) = (1, 24, 0, 1); // 100MHz -> 2.4GHz
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// used by Satellite - HMC830 is clocked by recovered clock
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// (or a clock of the same frequency derived from the same oscillator)
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#[cfg(all(hmc830_ref = "125", rtio_frequency = "125.0"))]
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const DIV: (u32, u32, u32, u32) = (2, 32, 0, 1); // 125MHz -> 2.0GHz
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#[cfg(all(hmc830_ref = "150", rtio_frequency = "150.0"))]
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@ -113,177 +113,6 @@ class RTMCommon:
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
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"""
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DRTIO master with local DAC/SAWG channels.
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"""
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"drtioaux": 0x14000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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RTMCommon.__init__(self)
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add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
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self.config["HMC830_REF"] = "100"
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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# ensure pins are properly biased and terminated
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si5324_clkout = platform.request("cdr_clk_clean", 0)
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self.specials += Instance(
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"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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attr={("DONT_TOUCH", "true")})
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self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
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self.csr_devices.append("ad9154_crg")
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self.comb += platform.request("sfp_tx_disable", 1).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=self.ad9154_crg.refclk,
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data_pads=[platform.request("sata"), platform.request("sfp", 1)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gth = self.drtio_transceiver.gths[0]
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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self.drtio_transceiver.cd_rtio.clk.attr.add("keep")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk)
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for gth in self.drtio_transceiver.gths[1:]:
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gth.rxoutclk)
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platform.add_false_path_constraints(
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self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
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platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
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self.drtio_transceiver.cd_rtio.clk)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs +
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self.ad9154_1.sawgs
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for phy in sawg.phys)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + drtio_cri,
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enable_routing=True)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
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platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
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self.csr_devices.append("sysref_sampler")
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self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
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self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
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def workaround_us_lvds_tristate(platform):
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# Those shoddy Kintex Ultrascale FPGAs take almost a microsecond to change the direction of a
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# LVDS I/O buffer. The application has to cope with it and this cannot be handled at static
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@ -601,7 +430,7 @@ def main():
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soc_sayma_amc_args(parser)
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parser.set_defaults(output_dir="artiq_sayma")
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parser.add_argument("-V", "--variant", default="satellite",
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help="variant: masterdac/master/satellite "
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help="variant: master/satellite "
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"(default: %(default)s)")
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parser.add_argument("--rtm-csr-csv",
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default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
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@ -613,9 +442,7 @@ def main():
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args = parser.parse_args()
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variant = args.variant.lower()
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if variant == "masterdac":
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cls = MasterDAC
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elif variant == "master":
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if variant == "master":
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cls = lambda with_sawg, **kwargs: Master(**kwargs)
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elif variant == "satellite":
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cls = Satellite
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