3a7819704a
rtio: support direct 64-bit now CSR in KernelInitiator
2020-04-26 16:04:32 +08:00
d19f28fa84
kasli: v2 clocking WIP, remove SFP LEDs from RTIO
2020-04-23 23:02:18 +08:00
ea79ba4622
ttl_serdes: detect edges on short pulses
...
Edges on pulses shorter than the RTIO period were missed because the
reference sample and the last sample of the serdes word are the same.
This change enables detection of edges on pulses as short as the
serdes UI (and shorter as long as the pulse still hits a serdes sample
aperture).
In any RTIO period, only the leading event corresponding to the first
edge with slope according to sensitivity is registerd. If the channel is
sensitive to both rising and falling edges and if the pulse is contained
within an RTIO period, or if it is sensitive only to one edge slope and
there are multiple pulses in an RTIO period, only the leading event is
seen. Thus this possibility of lost events is still there. Only the
conditions under which loss occurs are reduced.
In testing with the kasli-ptb6 variant, this also improves resource
usage (a couple hundred LUT) and timing (0.1 ns WNS).
2020-04-13 13:21:03 +02:00
ec7b2bea12
sayma: round FTW like Urukul in JDCGSyncDDS
2020-04-08 15:00:33 +08:00
0f4be22274
sayma: add simple sychronized DDS for testing
2020-04-08 14:13:54 +08:00
61d4614b61
sayma: fix/cleanup DRTIO-DAC sync interaction
2020-04-06 22:34:05 +08:00
ffd3172e02
sayma: move SYSREF DDMTD to RTM ( #795 )
2020-04-06 00:01:28 +08:00
e803830b3b
fastino: support wide RTIO interface and channel groups
2020-03-05 17:55:04 +00:00
6d26def3ce
sayma: drive filtered_clk_sel on master variant
2020-02-06 22:28:49 +08:00
c7de1f2e6b
metlino: drive clock muxes
2020-02-05 00:06:34 +08:00
dfa033eb87
wrpll: new collector from Weida/Tom
2020-01-24 10:31:52 +08:00
dee16edb78
wrpll: DDMTD sampler double latching
2020-01-22 19:16:26 +08:00
248230a89e
fastino: style
2020-01-20 13:25:00 +01:00
2c4e5bfee4
fastino: add [WIP]
2020-01-20 13:25:00 +01:00
01a6e77d89
mirny: add
...
* This targets unrelease CPLD gateware (https://github.com/quartiq/mirny/issues/1 )
* includes initial coredevice driver, eem shims, and kasli_generic tooling
* addresses the ARTIQ side of #1130
* Register abstraction to be written
Signed-off-by: Robert Jördens <rj@quartiq.de>
2020-01-20 13:13:08 +01:00
6c3e71a83a
wrpll: cleanup
2020-01-18 09:43:43 +08:00
344f8bd12a
wrpll: collector patch from Weida
2020-01-18 09:42:58 +08:00
6c948c7726
sayma: RF switch control is active-low on Basemod, invert
2020-01-16 08:59:52 +08:00
50302d57c0
wrpll: more careful I2C timing
2020-01-14 20:03:46 +08:00
105dd60c78
wrpll: ADPLLProgrammer mini test bench and fixes
2020-01-14 16:52:25 +08:00
3242e9ec6c
wrpll: loop test
2020-01-13 22:31:57 +08:00
8ec0f2e717
wrpll: implement ADPLLProgrammer
2020-01-13 22:30:11 +08:00
d685619bcd
wrpll: collector code modifications from Weida
2020-01-13 20:42:41 +08:00
a666766f38
wrpll: add ADPLL offset registers
2019-12-30 22:19:42 +08:00
5c6e394928
ddmtd: add collector
2019-12-30 22:17:44 +08:00
f57f235dca
wrpll: new frequency meter
...
As per Mattermost discussion with Tom.
2019-12-30 19:47:57 +08:00
9e15ff7e6a
wrpll: improve DDMTD deglitcher
2019-12-30 16:56:06 +08:00
b7f1623197
sayma_rtm: connect attenuator shift registers in series
2019-12-20 18:58:31 +08:00
1c9cbe6285
sayma_rtm: add basemod attenuators on RTIO
2019-12-20 15:25:55 +08:00
6ee15fbcae
sayma_rtm: basemod RF switches
2019-12-18 10:33:29 +08:00
52112d54f9
kasli_generic: expose peripheral_processors dictionary. Closes #1403
2019-12-10 10:30:06 +08:00
150a02117c
sayma_rtm: drive clk_src_ext_sel
2019-12-09 19:47:50 +08:00
307a6ca140
gth_ultrascale: make OBUFDS_GTE3 work
...
https://www.xilinx.com/support/answers/67919.html
2019-12-09 18:13:22 +08:00
2b5213b013
wrpll: constrain clocks
2019-12-09 12:26:44 +08:00
05e2e1899a
wrpll: update OBUFDS_GTE2 comment
...
Seems O can fan out simultaneously to transceiver and fabric.
Kasli is using ODIV2 for no particular reason.
2019-12-09 11:58:54 +08:00
4148efd2ee
wrpll: implement filters and connect to Si549
2019-12-09 11:47:29 +08:00
d43fe644f0
wrpll: stabilize DDMTDSamplerGTP
2019-12-09 11:47:14 +08:00
0499f83580
wrpll: helper clock sanity check
2019-12-08 23:46:33 +08:00
46a776d06e
sayma: introduce WRPLL on RTM
2019-12-08 15:30:00 +08:00
883310d83e
sayma_rtm: si5324 -> cdrclkc
2019-12-08 14:26:05 +08:00
57a5bea43a
sayma_rtm: support setting RTIO frequency
2019-12-08 11:45:31 +08:00
da9237de53
wrpll: support differential DDMTD inputs
2019-12-07 18:18:57 +08:00
7098854b0f
wrpll: share DDMTD counter
2019-12-04 19:05:56 +08:00
05c5fed07d
suservo: stray comma
2019-12-03 08:38:07 +00:00
56074cfffa
suservo: support operating with one urukul
...
implemented by wiring up the second Urukul to dummy pins
Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-12-02 11:30:20 +01:00
86e1924493
kasli_generic: support external reference on masters
2019-11-30 07:34:41 +00:00
eb271f383b
wrpll: add DDMTD cores
2019-11-28 22:03:50 +08:00
2e55e39ac7
wrpll: use spaces to indent
2019-11-28 17:40:25 +08:00
354d82cfe3
wrpll: drive helper clock domain
2019-11-28 17:40:00 +08:00
68cab5be8c
si549: cleanups
2019-11-28 16:36:59 +08:00
4832bfb08c
wrpll: i2c functions, select_recovered_clock placeholder
2019-11-27 21:21:00 +08:00
c536f6c4df
sayma_amc: output ddmtd_rec_clk
2019-11-20 19:16:04 +08:00
ae50da09c4
drtio/gth_ultrascale: support OBUFDS_GTE3
2019-11-20 19:15:50 +08:00
fe0c324b38
sayma: integrate si549 core
2019-11-20 17:37:16 +08:00
fa41c946ea
wrpll: si549 fixes
2019-11-20 17:04:24 +08:00
c5dbab1929
gateware: move wrpll to drtio
2019-11-20 14:43:08 +08:00
David Nadlinger
bc3b55b1a8
gateware/eem: Force IOB=TRUE on Urukul SYNC output
...
Without this, the final register in the SYNC signal TTLClockGen
isn't (always) placed in the I/O tile, leading to more jitter
than necessary, and causing "double window" artefacts. See
sinara-hw/Urukul#16 for more details.
(Patch based on work by Weida Zhang, testing by various members
of the community in Oxford and elsewhere.)
2019-11-05 17:14:07 +08:00
98854473dd
sayma_amc: use all transceivers on master ( #1230 )
2019-11-02 12:12:32 +08:00
42af76326f
kasli: enlarge integrated CPU SRAM for DRTIO masters
...
Required by the bootloader netboot support.
2019-11-01 10:15:13 +08:00
228e44a059
sayma: enable Ethernet on DRTIO satellite variant
...
So that netboot can be used in bootloader.
2019-10-30 21:39:00 +08:00
dc71039934
sayma, metlino: increase integrated_sram_size on Ethernet-enabled variants
2019-10-30 21:36:00 +08:00
462cf5967e
bootloader: add netboot support
2019-10-30 21:23:42 +08:00
8fa3c6460e
sayma_amc: set direction of external TTL buffer according to RTIO PHY OE
2019-10-16 18:48:50 +08:00
37d0a5dc19
rtio/ttl: expose OE
2019-10-16 18:48:20 +08:00
bc060b7f01
style
2019-10-16 18:18:11 +08:00
21a1c6de3f
sayma: use SFP0 for DRTIO master
2019-10-16 17:53:40 +08:00
314d9b5d06
kasli: default to 125MHz frequency for DRTIO
...
This is the consistent and most common option. Sayma will also eventually move to it.
2019-10-08 12:59:52 +08:00
4df2c5d1fb
sayma: prepare for SYSREF align
...
We will try DDMTD on the AMC first, as this is simpler and perhaps will work on v2 after the power supply fixes.
2019-10-08 12:30:47 +08:00
03007b896e
sayma_amc: sma -> mcx
2019-10-07 20:31:35 +08:00
97a0dee3e8
jesd204: remove ibuf_disable
...
We use the MOSFET to mute the HMC7043 noise on hardware v2 instead.
2019-10-06 22:26:31 +08:00
f8e4cc37d0
sayma_rtm: reset and detect DACs
2019-10-06 20:15:27 +08:00
f62dc7e1d4
sayma: refactor JESD DAC channel groups
2019-10-06 20:15:09 +08:00
1c6c22fde9
sayma_amc: HMC830_REF moved to RTM side
2019-10-06 18:15:37 +08:00
e6ff44301b
sayma_amc: cleanup (v2.0 only)
2019-10-06 18:11:43 +08:00
e9b81f6e33
remove serwb
...
DRTIO is a better solution
2019-10-06 18:10:23 +08:00
7cd02d30b7
sayma_rtm_drtio: replace sayma_rtm
2019-10-06 17:59:53 +08:00
b3b85135a3
sayma_rtm_drtio: add DDMTD core, move specific cores out of SatelliteBase
2019-10-06 17:59:11 +08:00
346c985347
sayma_rtm_drtio: use artiq_sayma folder
2019-10-06 17:30:08 +08:00
4198033657
sayma_rtm_drtio: cleanup (v2.0 only)
2019-10-06 16:42:34 +08:00
5612b31860
sayma_rtm_drtio: add HMC clock chip and DAC control
2019-10-06 16:15:24 +08:00
a8cf4c2b18
sayma_rtm: hwrev v2.0 by default
2019-10-06 13:25:30 +08:00
bb5ff46f7d
Merge branch 'wrpll'
2019-10-05 10:24:11 +08:00
7b95814cf5
sayma_amc: refactor, add SimpleSatellite variant
2019-10-05 10:24:06 +08:00
58b7bdcecc
sayma_amc: refactor RTM FPGA code
2019-10-05 10:24:06 +08:00
96fc4a21e8
sayma_amc: remove dummy FPGA pin assignment testing code
2019-10-05 10:24:06 +08:00
6aa68e1715
sayma_rtm2: select filtered clock from Si5324
2019-10-04 22:56:16 +08:00
6cb0f5de59
sayma_amc: enable DRTIO switching
2019-10-04 22:55:23 +08:00
0cf8a46bbd
sayma_amc2: select filtered clock from Si5324
2019-10-04 21:28:26 +08:00
f0e87d2e59
grabber: remove unused code
2019-09-20 15:26:12 +02:00
991c686d72
kasli_generic,eem: print RTIO channels in hex like artiq_ddb_template
2019-09-11 15:51:53 +08:00
7492a59f6d
kasli_generic: add SUServo support ( #1343 )
2019-09-11 11:12:48 +08:00
21021beb08
kasli: remove opticlock (moved to kasli_generic)
2019-09-09 15:03:10 +08:00
cfb5ef5548
kasli_generic: add Novogorny support
2019-09-09 14:54:34 +08:00
1fb317778a
eem/grabber: allow third EEM to be specified
2019-08-29 18:58:12 +08:00
959679d8b7
wrpll: add I2CMasterMachine
2019-08-27 18:02:05 +08:00
1fd2322662
wrpll/thls: implement global writeback
2019-08-15 23:16:17 +08:00
24082b687e
wrpll/filters: clean up and make compatible with thls
2019-08-15 17:58:22 +08:00
9331fafab0
wrpll/filters: new code from Weida
2019-08-15 17:24:40 +08:00
5c3974c265
wrpll/thls: fix opcode decoding
2019-08-15 17:12:48 +08:00
19620948bf
wrpll/thls: implement signed numbers
2019-08-15 17:04:17 +08:00
efc43142a6
wrpll/thls: implement min/max
2019-08-15 16:42:59 +08:00
44969b03ad
wrpll/thls: rework instruction decoding
2019-08-15 15:55:13 +08:00
2776c5b16b
wrpll/thls: support mulshift
2019-08-15 15:07:13 +08:00
f861459ace
wrpll: add filter algorithms (WIP)
2019-08-02 13:23:16 +08:00
7a5dcbe60e
wrpll/thls: support processor start/stop
2019-07-24 18:51:33 +08:00
623446f82c
wrpll/thls: simple simulation demo
2019-07-20 18:50:57 +08:00
831b3514d3
wrpll/thls: stop at return statement
2019-07-19 16:27:29 +08:00
34222b3f38
wrpll: encode thls program
2019-07-09 17:56:14 +08:00
5f461d08cd
wrpll: add simple thls compiler
2019-07-09 16:07:31 +08:00
e4fff390a8
si590 -> si549
...
Had mistaken the part numbers.
2019-07-07 09:39:55 +08:00
dceb5ae501
wrpll: Si590 I2C mux, CDC
2019-07-05 23:42:37 +08:00
f8dba7ae35
rtio: use BlindTransfer from Migen
2019-07-05 18:46:18 +08:00
David Nadlinger
0353966ef7
gateware/suservo: Sign-extend data on RTIO read-back
...
See GitHub #1327 for original patch by Brad Bondurant.
2019-06-14 23:46:16 +01:00
David Nadlinger
720838a23e
gateware/suservo: Avoid magic number for activation delay width
...
Mostly for documentation purposes; 8 bits ought to be enough for
everyone.
2019-06-14 23:45:40 +01:00
43e58c939c
sayma: drop MasterDAC
...
This seemed like a good idea then, but it introduces complexity, corner cases, and additional testing difficulties.
Now Sayma works fine with Kasli as a master, which is simpler.
2019-06-14 14:06:16 +08:00
b04e15741b
drop SI5324_SAYMA_REF
2019-06-14 14:03:48 +08:00
bc2cfd77f5
metlino: add EEMs
2019-05-19 18:16:00 +08:00
cdef50c0dd
sayma_amc: Urukul v1.3
2019-05-19 16:54:38 +08:00
9dcaae6395
metlino: use variant output directory
2019-05-19 16:24:51 +08:00
b4779969d0
metlino: work around vivado bug ( #1230 )
2019-05-19 11:27:27 +08:00
874542f33f
add Metlino support
2019-05-19 10:57:43 +08:00
hartytp
cfe1f56f73
suservo: add some more comments to the RTServoMem to clarify the RTIO interface ( #1323 )
2019-05-17 16:12:35 +01:00
fda3cb2482
kasli_generic: add edge counter support
2019-05-09 17:19:11 +08:00
ead9a42842
kasli: remove VLBAIMaster, VLBAISatellite variants
2019-05-08 15:58:25 +00:00
0c9b810501
kasli: remove PTB/PTB2/LUH/HUB variants
...
see sinara-systems and nix-scripts repos
2019-05-08 15:51:18 +00:00
1d2cc60e0d
kasli_generic: support ext_ref
2019-05-08 15:51:18 +00:00
David Nadlinger
4d215cf541
firmware: Add Si5324 config for 125 MHz ext ref
...
PLL divider settings as suggested by DSPLLsim 5.1.
2019-04-15 22:22:19 +01:00
97b7ed557b
sayma_amc: do not use SFP0 (now used for Ethernet)
2019-04-12 18:47:18 +08:00
4499ef1748
kasli: only add moninj core if there are probes to monitor
2019-03-24 14:09:52 +08:00
5d31cf2268
sayma_rtm2: si5324_clkout -> cdr_clk_clean
2019-03-23 13:48:36 +08:00
560849e693
sayma_amc: add DRTIO transceiver on rtm_amc_link for v2 hardware
2019-03-23 13:41:22 +08:00
bbb8c00518
sayma_amc: default to satellite variant
2019-03-23 13:37:55 +08:00
18fbe0b081
sayma_rtm_drtio: support v2 hardware
2019-03-23 13:31:28 +08:00
c7205ad82f
sayma_rtm: preliminary v2 support
2019-03-23 12:37:03 +08:00
33b28f6e56
sayma_amc: add placeholder code to use DDMTD signals on v2 hardware
2019-03-21 17:37:22 +08:00
2ec5a58c59
sayma_amc: si5324_clkout -> cdr_clk_clean
2019-03-21 14:09:33 +08:00
e47ba4b35e
kasli_generic: fix identifier string
2019-03-08 19:57:20 +08:00
62c7f75a9e
sayma_amc: support hardware revisions
2019-02-25 23:49:45 +08:00
d45249197c
siphaser: improve ultrascale clock routing
2019-02-25 23:00:01 +08:00
de3992bbdd
kasli: remove HUST variants (supported by kasli_generic)
2019-02-23 15:44:17 +08:00
791f830ef6
kasli_generic: support DRTIO
2019-02-23 15:41:05 +08:00
1c35c051a5
kasli: remove variants supported by generic builder
2019-02-22 23:08:49 +08:00
8edc2318ab
style
2019-02-22 17:19:20 +08:00
6ad2e13515
kasli: add generic builder (WIP)
2019-02-12 19:18:09 +08:00
ff4e4f15ed
kasli: expose base SoC classes
2019-02-12 18:33:27 +08:00
1cfd26dc2e
kasli: add UNSW variant
2019-02-08 17:51:51 +08:00
3e8fe3f29d
suservo: fix permissions
2019-02-08 14:54:02 +08:00
hartytp
87e85bcc14
suservo: fix coefficient data writing
...
Signed-off-by: Thomas Harty <thomas.harty@physics.ox.ac.uk>
2019-02-07 14:47:11 +01:00
b56c7cec1e
kasli: use 100MHz RTIO and 800MHz Urukul frequencies on Berkeley target
...
Urukul sync is not reliable at 125/1000
2019-02-05 11:24:45 +08:00
ea431b6982
sayma_rtm: use 150MHz RTIO freq for DDMTD
2019-01-31 20:43:44 +08:00
ec230d6560
sayma: move SYSREF DDMTD to the RTM
...
Put RTM Si5324 into bypass mode before running.
Needs rework to cut RTM Si5324 reset trace.
Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315.
Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic).
2019-01-31 20:39:33 +08:00
8119000982
sayma_rtm_drtio: use Si5324 soft reset
...
Needs easy board rework to cut trace at pin 1 of Si5324.
The Si5324 contains an internal pull-up on that pin.
Allows using Si5324 + HMC7043 chips at the same time.
Allows the Si5324 bypass hack for DDMTD experiments on the RTM.
2019-01-31 19:43:54 +08:00
d3c608aaec
jesd204sync: reset and check lock status of DDMTD helper PLL in firmware
2019-01-31 15:11:16 +08:00
c591009220
sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler
...
Better visibility, better diagnostics, allows some changing of SYSREF frequency while keeping the same gateware.
2019-01-29 23:30:01 +08:00
9ae57fd51e
sayma: pass rtio_clk_freq to DDMTD core
2019-01-29 15:06:45 +08:00
47312e55d3
sayma: set RTIO_FREQUENCY in MasterDAC
2019-01-28 13:43:28 +08:00
443d6d8688
sayma_amc: pass RTIO clock frequency to SiPhaser
2019-01-28 09:49:03 +08:00
81b0046f98
ddmtd: add deglitchers
2019-01-27 20:38:41 +08:00
8632b553d2
ddmtd: use IOB register to sample input
2019-01-27 09:50:02 +08:00
9966e789fc
sayma: simplify Ultrascale LVDS T false path
...
Recommended by Xilinx.
2019-01-25 23:40:48 +08:00
359fb1f207
sayma: fix DDMTD STA
2019-01-25 23:39:19 +08:00
cb04230f86
sayma: SYSREF setup/hold validation demonstration
...
This also removes the standalone target as the ISERDES used
for setup/hold check requires the fine RTIO clock, which in turn
requires a DRTIO transceiver due to the Ultrascale TPWS bug.
2019-01-25 16:58:58 +08:00
3356717316
sayma: DDMTD SYSREF measurement demonstration
2019-01-25 16:00:31 +08:00
4941fb3300
sayma: 2.4GHz DAC clocking (4X interpolation)
...
* gets another clock divider out of the way
* gets one cycle within range of the HMC7043 analog delay alone
* SYSREF/RTIO alignment removed, to be replaced with DDMTD-based scheme
2019-01-25 13:47:04 +08:00
07b5b0d36d
kasli: adapt Master target to new hardware
2019-01-24 18:27:15 +08:00
154269b77a
kasli: fix HUST satellite Urukul
2019-01-23 17:59:43 +08:00
d7e6f104d2
kasli: add HUST variants
2019-01-23 14:11:51 +08:00
81f2b2c864
kasli: remove unpopulated Tester EEMs
...
* matches hardware and avoids issues with programs that process the DDB (e.g. kasli_tester)
* shortens compilation times
2019-01-23 12:14:44 +08:00
9ee5fea88d
kasli: support optional SATA port for DRTIO
2019-01-22 18:06:48 +08:00
bff8c8cb05
kasli: add Berkeley variant
2019-01-21 17:44:17 +08:00
a2ff2cc173
sayma_amc: use more selective IOBUFDS false path
2019-01-19 11:47:50 +08:00
David Nadlinger
1c71ae636a
examples: Add edge counters to kasli_tester variant
...
This enables test_edge_counter on the CI system.
2019-01-15 10:55:07 +00:00
David Nadlinger
a565f77538
Add gateware input event counter
2019-01-15 10:55:07 +00:00
4cb9f77fd8
sayma_amc: fix Master timing constraints
2019-01-13 13:53:07 +08:00
9b213b17af
sayma_amc: forward RTM UART in Master variant as well
2019-01-09 18:57:57 +08:00
c7b18952b8
sayma_amc: work around Ultrascale LVDS Toutbuf_delay_td_pad
2019-01-09 13:47:08 +08:00
3217488824
add Sayma RTM DRTIO target
2019-01-07 00:13:47 +08:00
66b3132c28
sayma_amc: fix RTIO TSC instantiation
2019-01-06 14:54:32 +08:00
cf9447ab77
rtio/cri: remove unneeded CSR management
2019-01-05 23:40:45 +08:00
2100a8b1f1
sayma_amc: more fighting with vivado timing analyzer
2019-01-05 12:25:30 +08:00
62d7c89c48
sayma_amc: use high-resolution TTL on SMAs ( #792 )
2019-01-03 20:50:38 +08:00
0972d61e81
ttl_serdes_ultrascale: use GTH clock domains
2019-01-03 20:50:04 +08:00
f007895fad
drtio/gth_ultrascale: fix rtiox clock domain
2019-01-03 20:49:38 +08:00
10ebf63c47
jesd204_tools: get the Vivado timing analyzer to behave
2019-01-03 20:22:35 +08:00
4af8fd6a0d
ttl_serdes_ultrascale: fix Input
2019-01-03 20:14:54 +08:00
175f8b8ccc
drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT ( #792 )
2019-01-03 20:14:18 +08:00
77126ce5b3
kasli: use hwrev 1.1 by default for DRTIO examples
2019-01-02 23:04:20 +08:00
ab9ca0ee0a
kasli: use 150MHz for DRTIO by default (Sayma compatibility)
2019-01-02 23:03:57 +08:00
cc58318500
siphaser: autocalibrate skew using RX synchronizer
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* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
2019-01-02 22:29:27 +08:00
f5cda3689e
sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant
2019-01-02 16:46:16 +08:00
6df4ae934f
eem: name the servo submodule
...
This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos
close #1201
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
7e14f3ca4e
compiler,gateware: atomic now stores
2018-12-02 05:06:46 +08:00
c56c0ba41f
rtio/dds: use write-only RT2WB
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This saves one address bit and prevents issues with AD9914 and 8-bit addresses.
2018-11-26 07:38:15 +08:00
09141e5bee
rtio/wishbone: support write-only interface
2018-11-26 07:38:06 +08:00
450a035f9e
suservo: move overflowing RTIO address bits into data
2018-11-26 06:54:20 +08:00
ae8ef18f47
rtlink: sanity-check parameters
2018-11-26 01:14:02 +08:00
53e79f553f
Merge branch 'master' into new
2018-11-19 11:54:50 +08:00
78d4b3a7da
gateware/targets: expose variant lists
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This allows writing scripts that build all variants.
2018-11-17 22:10:20 +08:00
1b841805f6
Merge branch 'master' into new
2018-11-16 15:20:32 +08:00
2af6edb8f5
eem: fix reset/sync in suservo
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-13 13:00:54 +00:00
1f7858b80b
test/dsp: fix rtio_output
2018-11-09 22:11:44 +08:00
e509ab8553
test/dsp: use absolute import path
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Avoids "ImportError: attempted relative import with no known parent package"
when doing a simple "python -m unittest test_XXX.py".
2018-11-09 22:10:46 +08:00
c990b5e4f1
Merge remote-tracking branch 'origin/master' into new
2018-11-08 20:21:56 +08:00
f74dda639f
drtio: 8-bit address
2018-11-08 18:36:20 +08:00
8caea0e6d3
gateware,runtime: optimize RTIO kernel interface further
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* now pinning (TODO: atomicity)
* for inputs, merge request and timeout registers
2018-11-08 18:29:24 +08:00
aadf5112b7
rtio: remove incorrect comment
2018-11-08 00:02:44 +08:00
3d0c3cc1cf
gateware,runtime: optimize RTIO output interface
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* reduce address to 8 bits
* merge core, channel and address into 32-bit pre-computable "target"
* merge we register into data register
2018-11-07 23:39:58 +08:00
ad0254c17b
Merge branch 'switching125' into new
2018-11-07 22:03:18 +08:00
efd735a6ab
Revert "drtio: monitor RTIOClockMultiplier PLL ( #1155 )"
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This reverts commit 469a66db61
2018-11-07 22:01:03 +08:00
ba4bf6e59b
kasli: don't pass rtio pll feedback through bufg
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UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:58:55 +00:00
b6e4961b0f
kasli: lower RTIO clock jitter
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* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:43:19 +00:00
e17e458c58
ptb2: add sync to urukul0 for ad9910 usage
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 10:06:51 +00:00
31f68ddf6c
Merge branch 'urukul-sync'
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* urukul-sync: (29 commits)
urukul: flake8 [nfc]
ad9910: flake8 [nfc]
urukul/ad9910 test: remove unused import
test_urukul: relax speed
urukul,ad9910: print speed metrics
kasli: add PTB2 (external clock and SYNC)
kasli: add sync to LUH, HUB, Opticlock
kasli_tester: urukul0 mmcx clock defunct
test_ad9910: relax ifc mode read
tests: add Urukul-AD9910 HITL unittests including SYNC
ad9910: add init bit explanation
test: add Urukul CPLD HITL tests
ad9910: fiducial timestamp for tracking phase mode
ad9910: add phase modes
ad9910: fix pll timeout loop
tester: add urukul sync
ptb: back out urukul-sync
ad9910: add IO_UPDATE alignment and tuning
urukul: set up sync_in generator
ad9910: add io_update alignment measurement
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close #1143
2018-11-05 19:54:30 +01:00
32d538f72b
kasli: add PTB2 (external clock and SYNC)
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:16 +01:00
d8a5951a13
kasli: add sync to LUH, HUB, Opticlock
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for #1143 , also add missing LUH device db
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:14 +01:00
4269d5ad5c
tester: add urukul sync
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:52 +01:00
60d3bc63a7
ptb: back out urukul-sync
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... for backwards compatibility.
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:50 +01:00
3538444876
urukul: add sync_in to eem0-7 name
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:32 +01:00
0433e8f4fe
urukul: add sync_in generator
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
bc4a8157c0
kasli: add tsinghua2
2018-11-01 18:26:37 +08:00
48a142ed63
use FutureWarning instead of DeprecationWarning
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DeprecationWarning is disabled by default and too easy to ignore.
2018-10-21 12:14:51 +08:00
6357a50d33
kasli: update nudt variant
2018-10-15 18:04:57 +08:00
469a66db61
drtio: monitor RTIOClockMultiplier PLL ( #1155 )
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Debugging by Tom Harty
2018-10-08 14:50:02 +02:00
86fe6b0594
kasli: add NUDT variant
2018-10-04 23:20:09 +08:00
a89bd6b684
kasli: swap Urukul EEMs for Tester
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Updated to Urukul 1.3.
2018-10-04 23:19:31 +08:00
9f96b6bcda
kasli: use 125MHz DRTIO freq for testing
2018-10-04 10:41:01 +08:00
969a305c5a
Merge branch 'master' into switching125
2018-10-04 10:08:42 +08:00
d0ee2c2955
opticlock: external 100 MHz
2018-09-28 19:05:18 +02:00
3b3fddb5a4
kasli: add mitll2
2018-09-27 23:21:52 +08:00
b92350b0f6
drtio: monitor RTIOClockMultiplier PLL ( #1155 )
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Debugging by Tom Harty
2018-09-26 10:52:08 +08:00
212892d92f
style
2018-09-26 10:13:33 +08:00
73f0de7c79
sayma: DRTIO master fixes
2018-09-20 11:15:45 +08:00
53a979e74d
rtio: cleanup resets
2018-09-20 10:58:38 +08:00
251d90c3d5
drtio: clear read request in satellite only after reply has been fully sent
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Otherwise, chan_sel become invalid before the end of the packet, which
can cause the interconnect to invalidate i_timestamp and i_data which results
in corruption of the end of the packet.
2018-09-20 08:53:45 +08:00
69d060b639
drtio: fix satellite i_status handling
2018-09-19 20:57:21 +08:00
b86b6dcc09
drtio: add switching input test
2018-09-19 17:50:29 +08:00
08be176369
drtio: fix satellite i_status handling
2018-09-19 17:50:18 +08:00
3d965910f7
Revert "drtio: implement per-destination underflow margins"
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This reverts commit 142c952e3d
2018-09-19 17:05:48 +08:00
142c952e3d
drtio: implement per-destination underflow margins
2018-09-19 17:03:15 +08:00
970d1bf147
drtio: add switching unittest
2018-09-18 15:27:52 +08:00
eda15a596c
drtio: add buffering to repeater
2018-09-18 15:27:25 +08:00
2b44786f73
drtio: add repeater input support
2018-09-17 23:45:27 +08:00
d38755feff
drtio: implement destination state checks on operations
2018-09-15 15:55:45 +08:00
cd61ee858c
kasli: fix satellite TSC instantiation
2018-09-15 14:06:54 +08:00
1ef39a98a7
drtio: implement per-destination buffer space
2018-09-13 16:16:32 +08:00
0befec7d26
drtio: improve repeater error reports
2018-09-12 20:54:01 +08:00
420e1cb1d0
cri: fix firmware routing table access
2018-09-12 18:08:16 +08:00
5bcd40ff59
cri: fix routing table depth
2018-09-12 17:30:55 +08:00
edf403b837
drtio: improve error reporting
2018-09-12 15:44:34 +08:00
95432a4ac1
drtio: remove old debugging features
2018-09-12 13:01:27 +08:00
