forked from M-Labs/artiq
wrpll: collector patch from Weida
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parent
833f428391
commit
344f8bd12a
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@ -113,19 +113,19 @@ class Collector(Module):
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self.tag_main = Signal(N)
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self.tag_main_update = Signal()
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self.output = Signal(N)
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self.output = Signal((N, True))
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self.output_update = Signal(N)
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# # #
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fsm = FSM()
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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tag_collector = Signal(N)
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fsm.act("IDLE",
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If(self.tag_main_update & self.tag_helper_update,
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NextValue(tag_collector, 0),
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NextState("IDLE")
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NextState("UPDATE")
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).Elif(self.tag_main_update,
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NextValue(tag_collector, self.tag_main),
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NextState("WAITHELPER")
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@ -137,19 +137,22 @@ class Collector(Module):
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fsm.act("WAITHELPER",
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If(self.tag_helper_update,
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NextValue(tag_collector, tag_collector - self.tag_helper),
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NextState("IDLE")
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NextState("UPDATE")
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)
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)
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fsm.act("WAITMAIN",
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If(self.tag_main_update,
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NextValue(tag_collector, tag_collector + self.tag_main),
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NextState("IDLE")
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NextState("UPDATE")
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)
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)
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fsm.act("UPDATE",
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NextValue(self.output, tag_collector),
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NextState("IDLE")
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)
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self.sync += [
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self.output_update.eq(0),
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If(self.tag_helper_update,
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self.output_update.eq(1),
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self.output.eq(tag_collector)
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self.output_update.eq(1)
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)
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]
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