forked from M-Labs/artiq
add Sayma RTM DRTIO target
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parent
b5501aaf00
commit
3217488824
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#!/usr/bin/env python3
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import argparse
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import os
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import subprocess
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import struct
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores.a7_gtp import *
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from misoc.targets.sayma_rtm import BaseSoC
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from misoc.integration.builder import Builder, builder_args, builder_argdict
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_serdes_7series
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import add_identifier
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from artiq import __artiq_dir__ as artiq_dir
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def fix_serdes_timing_path(platform):
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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class _RTIOClockMultiplier(Module, AutoCSR):
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def __init__(self, rtio_clk_freq):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
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clkfbout = Signal()
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clkfbin = Signal()
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rtiox4_clk = Signal()
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pll_locked = Signal()
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_RST=self.pll_reset.storage,
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o_LOCKED=pll_locked,
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p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
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o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
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p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
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),
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Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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class _SatelliteBase(BaseSoC):
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mem_map = {
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"drtioaux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq=150e6, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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**kwargs)
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add_identifier(self)
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platform = self.platform
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=disable_si5324_ibuf,
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i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
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o_O=si5324_clkout_buf)
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qpll_drtio_settings = QPLLSettings(
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refclksel=0b001,
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fbdiv=4,
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fbdiv_45=5,
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refclk_div=1)
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=qpll.channels[0],
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data_pads=[platform.request("sata", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += disable_si5324_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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self.submodules.drtioaux0 = coreaux
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self.csr_devices.append("drtioaux0")
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memory_address = self.mem_map["drtioaux"]
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.cd_sys.clk, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("hmc7043_reset"))
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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gtp = self.drtio_transceiver.gtps[0]
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.comb += self.drtiosat.cri.connect(self.local_io.cri)
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class Satellite(_SatelliteBase):
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def __init__(self, **kwargs):
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_SatelliteBase.__init__(self, **kwargs)
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self.rtio_channels = []
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phy = ttl_serdes_7series.Output_8X(self.platform.request("allaki0_rfsw0"))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_serdes_7series.Output_8X(self.platform.request("allaki0_rfsw1"))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(self.rtio_channels)
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class SatmanSoCBuilder(Builder):
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def __init__(self, *args, **kwargs):
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Builder.__init__(self, *args, **kwargs)
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firmware_dir = os.path.join(artiq_dir, "firmware")
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self.software_packages = []
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self.add_software_package("satman", os.path.join(firmware_dir, "satman"))
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def initialize_memory(self):
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satman = os.path.join(self.output_dir, "software", "satman",
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"satman.bin")
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with open(satman, "rb") as boot_file:
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boot_data = []
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unpack_endian = ">I"
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while True:
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w = boot_file.read(4)
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if not w:
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break
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boot_data.append(struct.unpack(unpack_endian, w)[0])
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self.soc.main_ram.mem.init = boot_data
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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builder_args(parser)
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parser.set_defaults(output_dir="artiq_sayma_rtm")
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args = parser.parse_args()
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soc = Satellite()
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builder = SatmanSoCBuilder(soc, **builder_argdict(args))
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try:
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builder.build()
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except subprocess.CalledProcessError as e:
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raise SystemExit("Command {} failed".format(" ".join(e.cmd)))
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if __name__ == "__main__":
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main()
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