forked from M-Labs/artiq
wrpll: improve DDMTD deglitcher
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dfad27125e
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@ -44,19 +44,23 @@ class DDMTDSamplerGTP(Module):
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]
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class DDMTDEdgeDetector(Module):
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def __init__(self, input_signal):
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self.rising = Signal()
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class DDMTDDeglitcherFirstEdge(Module):
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def __init__(self, input_signal, blind_period=128):
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self.detect = Signal()
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self.tag_correction = 0
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history = Signal(4)
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deglitched = Signal()
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self.sync.helper += history.eq(Cat(history[1:], input_signal))
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self.comb += deglitched.eq(input_signal | history[0] | history[1] | history[2] | history[3])
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deglitched_r = Signal()
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rising = Signal()
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input_signal_r = Signal()
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self.sync.helper += [
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deglitched_r.eq(deglitched),
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self.rising.eq(deglitched & ~deglitched_r)
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input_signal_r.eq(input_signal),
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rising.eq(input_signal & ~input_signal_r)
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]
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blind_counter = Signal(max=blind_period)
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self.sync.helper += [
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If(blind_counter != 0, blind_counter.eq(blind_counter - 1)),
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If(rising, blind_counter.eq(blind_period - 1)),
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self.detect.eq(rising & (blind_counter == 0))
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]
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@ -71,14 +75,14 @@ class DDMTD(Module, AutoCSR):
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# # #
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ed = DDMTDEdgeDetector(input_signal)
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self.submodules += ed
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deglitcher = DDMTDDeglitcherFirstEdge(input_signal)
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self.submodules += deglitcher
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self.sync.helper += [
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self.h_tag_update.eq(0),
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If(ed.rising,
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If(deglitcher.detect,
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self.h_tag_update.eq(1),
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self.h_tag.eq(counter)
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self.h_tag.eq(counter + deglitcher.tag_correction)
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)
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]
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