forked from M-Labs/artiq
urukul: add sync_in generator
for #1143 Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -115,6 +115,7 @@ class CPLD:
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:param spi_device: SPI bus device name
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:param io_update_device: IO update RTIO TTLOut channel name
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:param dds_reset_device: DDS reset RTIO TTLOut channel name
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:param sync_device: AD9910 SYNC_IN RTIO TTLClockGen channel name
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:param refclk: Reference clock (SMA, MMCX or on-board 100 MHz oscillator)
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frequency in Hz
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:param clk_sel: Reference clock selection. For hardware revision >= 1.3
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@ -122,8 +123,8 @@ class CPLD:
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internal MMCX. For hardware revision <= v1.2 valid options are: 0 -
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either XO or MMCX dependent on component population; 1 SMA. Unsupported
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clocking options are silently ignored.
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:param sync_sel: SYNC clock selection. 0 corresponds to SYNC clock over EEM
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from FPGA. 1 corresponds to SYNC clock from DDS0.
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:param sync_sel: SYNC_IN selection. 0 corresponds to SYNC_IN over EEM
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from FPGA. 1 corresponds to SYNC_IN from DDS0.
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:param rf_sw: Initial CPLD RF switch register setting (default: 0x0).
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Knowledge of this state is not transferred between experiments.
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:param att: Initial attenuator setting shift register (default:
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@ -134,7 +135,8 @@ class CPLD:
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kernel_invariants = {"refclk", "bus", "core", "io_update"}
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def __init__(self, dmgr, spi_device, io_update_device=None,
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dds_reset_device=None, sync_sel=0, clk_sel=0, rf_sw=0,
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dds_reset_device=None, sync_device=None,
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sync_sel=0, clk_sel=0, rf_sw=0,
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refclk=125e6, att=0x00000000, core_device="core"):
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self.core = dmgr.get(core_device)
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@ -147,6 +149,8 @@ class CPLD:
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self.io_update = _RegIOUpdate(self)
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if dds_reset_device is not None:
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self.dds_reset = dmgr.get(dds_reset_device)
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if sync_device is not None:
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self.sync = dmgr.get(sync_device)
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self.cfg_reg = urukul_cfg(rf_sw=rf_sw, led=0, profile=0,
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io_update=0, mask_nu=0, clk_sel=clk_sel,
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@ -289,3 +293,20 @@ class CPLD:
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SPIT_ATT_RD, CS_ATT)
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self.bus.write(self.att_reg)
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return self.bus.read()
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@kernel
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def set_sync_div(self, div):
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"""Set the SYNC_IN AD9910 pulse generator frequency
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and align it to the current RTIO timestamp.
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The SYNC_IN signal is derived from the coarse RTIO clock
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and the divider must be a power of two two.
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Configure ``sync_sel == 0``.
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:param div: SYNC_IN frequency divider. Must be a power of two.
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Minimum division ratio is 2. Maximum division ratio is 16.
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"""
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ftw_max = 1 << 4
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ftw = ftw_max//div
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assert ftw*div == ftw_max
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self.sync.set_mu(ftw)
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@ -87,36 +87,42 @@ device_db.update({
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"class": "SPIMaster",
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"arguments": {"channel": 27}
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},
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"ttl_urukul0_io_update": {
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"ttl_urukul0_sync": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 28}
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"class": "TTLClockGen",
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"arguments": {"channel": 28, "acc_width": 4}
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},
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"ttl_urukul0_sw0": {
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"ttl_urukul0_io_update": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 29}
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},
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"ttl_urukul0_sw1": {
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"ttl_urukul0_sw0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 30}
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},
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"ttl_urukul0_sw2": {
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"ttl_urukul0_sw1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 31}
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},
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"ttl_urukul0_sw3": {
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"ttl_urukul0_sw2": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 32}
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},
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"ttl_urukul0_sw3": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 33}
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},
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"urukul0_cpld": {
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"type": "local",
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"module": "artiq.coredevice.urukul",
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@ -124,6 +130,7 @@ device_db.update({
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"arguments": {
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"spi_device": "spi_urukul0",
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"io_update_device": "ttl_urukul0_io_update",
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"sync_device": "ttl_urukul0_sync",
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"refclk": 100e6,
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"clk_sel": 0
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}
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@ -150,13 +157,19 @@ device_db.update({
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 33}
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"arguments": {"channel": 34}
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},
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"ttl_urukul1_sync": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLClockGen",
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"arguments": {"channel": 35, "acc_width": 4}
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},
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"ttl_urukul1_io_update": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 34}
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"arguments": {"channel": 36}
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},
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"urukul1_cpld": {
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"type": "local",
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@ -190,13 +203,13 @@ device_db.update({
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 35}
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"arguments": {"channel": 37}
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},
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"led1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 36}
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"arguments": {"channel": 38}
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}
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})
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@ -206,19 +219,19 @@ device_db.update({
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"type": "local",
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"module": "artiq.coredevice.spi2",
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"class": "SPIMaster",
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"arguments": {"channel": 37}
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"arguments": {"channel": 39}
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},
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"ttl_zotino0_ldac": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 38}
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"arguments": {"channel": 40}
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},
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"ttl_zotino0_clr": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 40}
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"arguments": {"channel": 41}
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},
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"zotino0": {
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"type": "local",
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@ -148,7 +148,8 @@ class Urukul(_EEM):
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return ios
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@classmethod
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def add_std(cls, target, eem, eem_aux, ttl_out_cls, iostandard="LVDS_25"):
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def add_std(cls, target, eem, eem_aux, ttl_out_cls, sync_gen_cls=None,
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iostandard="LVDS_25"):
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cls.add_extension(target, eem, eem_aux, iostandard=iostandard)
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phy = spi2.SPIMaster(target.platform.request("urukul{}_spi_p".format(eem)),
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@ -157,7 +158,12 @@ class Urukul(_EEM):
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target.rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = target.platform.request("urukul{}_dds_reset".format(eem))
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target.specials += DifferentialOutput(0, pads.p, pads.n)
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pad = Signal(reset=0)
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target.specials += DifferentialOutput(pad, pads.p, pads.n)
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if sync_gen_cls is not None: # AD9910 variant and SYNC_IN from EEM
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phy = sync_gen_cls(pad, ftw_width=4)
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy))
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pads = target.platform.request("urukul{}_io_update".format(eem))
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phy = ttl_out_cls(pads.p, pads.n)
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@ -170,7 +176,6 @@ class Urukul(_EEM):
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target.submodules += phy
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target.rtio_channels.append(rtio.Channel.from_phy(phy))
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class Sampler(_EEM):
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@staticmethod
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def io(eem, eem_aux, iostandard="LVDS_25"):
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@ -516,8 +516,10 @@ class PTB(_StandaloneBase):
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eem.DIO.add_std(self, 2,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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eem.Sampler.add_std(self, 3, None, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 5, 4, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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eem.Urukul.add_std(self, 6, None, ttl_serdes_7series.Output_8X,
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ttl_simple.ClockGen)
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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