forked from M-Labs/artiq
suservo: add some more comments to the RTServoMem to clarify the RTIO interface (#1323)
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@ -25,7 +25,31 @@ class RTServoCtrl(Module):
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class RTServoMem(Module):
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"""All-channel all-profile coefficient and state RTIO control
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interface."""
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interface.
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Servo internal addresses are internal_address_width wide, which is
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typically longer than the 8-bit RIO address space. We pack the overflow
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onto the RTIO data word after the data.
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Servo address space (from LSB):
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- IIR coefficient/state memory address, (w.profile + w.channel + 2) bits.
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If the state memory is selected, the lower bits are used directly as
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the memory address. If the coefficient memory is selected, the LSB
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(high_coeff) selects between the upper and lower halves of the memory
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location, which is two coefficients wide, with the remaining bits used
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as the memory address.
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- config_sel (1 bit)
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- state_sel (1 bit)
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- we (1 bit)
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destination | config_sel | state_sel
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----------------|------------|----------
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IIR coeff mem | 0 | 0
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IIR coeff mem | 1 | 0
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IIR state mem | 0 | 1
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config (write) | 1 | 1
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status (read) | 1 | 1
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"""
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def __init__(self, w, servo):
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m_coeff = servo.iir.m_coeff.get_port(write_capable=True,
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mode=READ_FIRST,
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@ -44,8 +68,6 @@ class RTServoMem(Module):
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assert w.coeff >= w.word
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# coeff, profile, channel, 2 mems, rw
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# this exceeds the 8-bit RTIO address, so we move the extra ("overflow")
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# address bits into data.
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internal_address_width = 3 + w.profile + w.channel + 1 + 1
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rtlink_address_width = min(8, internal_address_width)
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overflow_address_width = internal_address_width - rtlink_address_width
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@ -127,7 +127,7 @@ class IIR(Module):
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Each profile stores 8 values, each up to W.coeff bits wide, arranged as:
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[FTW1, B1, POW, CFG, OFFSET, A1, FTW0, B0]
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The lower 8 bits of CFG hold the ADC input channel index SEL.
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The bits from bit 8 up hold the IIR activation delay DLY.
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The subsequent 8 bits hold the IIR activation delay DLY.
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The back memory is 2*W.coeff bits wide and each value pair
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(even and odd address)
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are stored in a single location with the odd address value occupying the
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