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gateware/suservo: Avoid magic number for activation delay width 

Mostly for documentation purposes; 8 bits ought to be enough for
everyone.
This commit is contained in:
David Nadlinger 2019-06-11 20:45:54 +01:00
parent 53789ba9aa
commit 720838a23e
4 changed files with 13 additions and 14 deletions
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2
artiq/gateware/eem.py
View File

@ -513,7 +513,7 @@ class SUServo(_EEM):
t_conv=57 - 4, t_rtt=t_rtt + 4)
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
accu=48, shift=shift, channel=3,
profile=profile)
profile=profile, dly=8)
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
channels=adc_p.channels, clk=clk)
su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)

19
artiq/gateware/suservo/iir.py
View File

@ -20,6 +20,7 @@ IIRWidths = namedtuple("IIRWidths", [
"shift", # fixed point scaling coefficient for a1, b0, b1 (log2!) (11)
"channel", # channels (log2!) (3)
"profile", # profiles per channel (log2!) (5)
"dly", # the activation delay
])
@ -179,7 +180,7 @@ class IIR(Module):
IIRWidths(state=25, coeff=18, adc=16,
asf=14, word=16, accu=48, shift=11,
channel=3, profile=5)
channel=3, profile=5, dly=8)
X0 = ADC * 2^(25 - 1 - 16)
X1 = X0 delayed by one cycle
@ -372,20 +373,18 @@ class IIR(Module):
})
]
# selected adc (combinatorial from dat_r)
# selected adc and profile delay (combinatorial from dat_r)
# both share the same coeff word (sel in the lower 8 bits)
sel_profile = Signal(w.channel)
# profile delay (combinatorial from dat_r)
dly_profile = Signal(8)
dly_profile = Signal(w.dly)
assert w.channel <= 8
assert 8 + w.dly <= w.coeff
# latched adc selection
sel = Signal(w.channel, reset_less=True)
# iir enable SR
en = Signal(2, reset_less=True)
assert w.channel <= 8
assert w.profile <= len(dly_profile)
assert w.profile + 8 <= len(m_coeff.dat_r)
self.comb += [
sel_profile.eq(m_coeff.dat_r[w.coeff:]),
dly_profile.eq(m_coeff.dat_r[w.coeff + 8:]),
@ -417,7 +416,7 @@ class IIR(Module):
]
# internal channel delay counters
dlys = Array([Signal(len(dly_profile))
dlys = Array([Signal(w.dly)
for i in range(1 << w.channel)])
self._dlys = dlys # expose for debugging only
@ -430,7 +429,7 @@ class IIR(Module):
]
# latched channel delay
dly = Signal(len(dly_profile), reset_less=True)
dly = Signal(w.dly, reset_less=True)
# latched channel en_out
en_out = Signal(reset_less=True)
# latched channel en_iir

4
artiq/gateware/test/suservo/test_iir.py
View File

@ -8,10 +8,10 @@ from artiq.gateware.suservo import iir
def main():
w_kasli = iir.IIRWidths(state=25, coeff=18, adc=16,
asf=14, word=16, accu=48, shift=11,
channel=3, profile=5)
channel=3, profile=5, dly=8)
w = iir.IIRWidths(state=17, coeff=16, adc=16,
asf=14, word=16, accu=48, shift=11,
channel=2, profile=1)
channel=2, profile=1, dly=8)
def run(dut):
for i, ch in enumerate(dut.adc):

2
artiq/gateware/test/suservo/test_servo.py
View File

@ -13,7 +13,7 @@ class ServoSim(servo.Servo):
adc_p = servo.ADCParams(width=16, channels=8, lanes=4,
t_cnvh=4, t_conv=57 - 4, t_rtt=4 + 4)
iir_p = servo.IIRWidths(state=25, coeff=18, adc=16, asf=14, word=16,
accu=48, shift=11, channel=3, profile=5)
accu=48, shift=11, channel=3, profile=5, dly=8)
dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
channels=adc_p.channels, clk=1)