forked from M-Labs/artiq
kasli: support optional SATA port for DRTIO
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@ -850,7 +850,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, rtio_clk_freq=150e6, **kwargs):
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def __init__(self, rtio_clk_freq=150e6, enable_sata=False, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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@ -872,18 +872,29 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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drtio_data_pads = []
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if enable_sata:
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drtio_data_pads.append(platform.request("sata"))
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drtio_data_pads += [platform.request("sfp", i) for i in range(1, 3)]
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sfp_ctls = [platform.request("sfp_ctl", i) for i in range(1, 3)]
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self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=self.drtio_qpll_channel,
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data_pads=[platform.request("sfp", i) for i in range(1, 3)],
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += self.disable_si5324_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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if enable_sata:
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sfp_channels = self.drtio_transceiver.channels[1:]
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else:
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sfp_channels = self.drtio_transceiver.channels
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self.comb += [sfp_ctl.led.eq(channel.rx_ready)
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for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
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for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)]
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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@ -891,7 +902,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(2):
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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@ -999,7 +1010,7 @@ class _SatelliteBase(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq=150e6, **kwargs):
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def __init__(self, rtio_clk_freq=150e6, enable_sata=False, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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@ -1025,18 +1036,28 @@ class _SatelliteBase(BaseSoC):
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qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
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self.submodules += qpll
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drtio_data_pads = []
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if enable_sata:
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drtio_data_pads.append(platform.request("sata"))
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drtio_data_pads += [platform.request("sfp", i) for i in range(3)]
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sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
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self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=qpll.channels[0],
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data_pads=[platform.request("sfp", i) for i in range(3)],
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += disable_si5324_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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if enable_sata:
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sfp_channels = self.drtio_transceiver.channels[1:]
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else:
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sfp_channels = self.drtio_transceiver.channels
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self.comb += [sfp_ctl.led.eq(channel.rx_ready)
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for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
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for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)]
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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@ -1044,7 +1065,7 @@ class _SatelliteBase(BaseSoC):
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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self.drtio_cri = []
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for i in range(3):
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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