forked from M-Labs/artiq
metlino: add EEMs
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@ -11,7 +11,6 @@ from misoc.targets.metlino import *
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import eem
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from artiq.gateware import fmcdio_vhdci_eem
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_ultrascale
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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@ -124,20 +123,13 @@ class Master(MiniSoC, AMPSoC):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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#platform.add_extension(fmcdio_vhdci_eem.io)
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#platform.add_connectors(fmcdio_vhdci_eem.connectors)
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#fmcdio_dirctl = platform.request("fmcdio_dirctl")
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#for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
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# phy = ttl_simple.Output(s)
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# self.submodules += phy
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# rtio_channels.append(rtio.Channel.from_phy(phy))
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#eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
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# iostandard="LVDS")
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#eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
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# iostandard="LVDS")
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#eem.Zotino.add_std(self, 3, ttl_simple.Output,
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# iostandard="LVDS")
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#workaround_us_lvds_tristate(platform)
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eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
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iostandard="LVDS")
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eem.Urukul.add_std(self, 0, 1, ttl_simple.Output,
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iostandard="LVDS")
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eem.Zotino.add_std(self, 3, ttl_simple.Output,
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iostandard="LVDS")
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workaround_us_lvds_tristate(platform)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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