forked from M-Labs/artiq
rtio/cri: remove unneeded CSR management
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2c3510497b
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cf9447ab77
@ -121,7 +121,7 @@ class KernelInitiator(Module, AutoCSR):
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self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
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class CRIDecoder(Module, AutoCSR):
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class CRIDecoder(Module):
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def __init__(self, slaves=2, master=None, mode="async", enable_routing=False):
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if isinstance(slaves, int):
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slaves = [Interface() for _ in range(slaves)]
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@ -228,7 +228,7 @@ class CRIInterconnectShared(Module):
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self.submodules.decoder = CRIDecoder(slaves, shared, mode, enable_routing)
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def get_csrs(self):
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return self.switch.get_csrs() + self.decoder.get_csrs()
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return self.switch.get_csrs()
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class RoutingTableAccess(Module, AutoCSR):
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