forked from M-Labs/artiq
sayma_amc2: select filtered clock from Si5324
This commit is contained in:
parent
6f533727cb
commit
0cf8a46bbd
|
@ -381,6 +381,8 @@ class Satellite(BaseSoC, RTMCommon):
|
|||
]
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
||||
if self.hw_rev == "v2.0":
|
||||
self.comb += platform.request("filtered_clk_sel").eq(1)
|
||||
self.submodules.siphaser = SiPhaser7Series(
|
||||
si5324_clkin=platform.request("si5324_clkin"),
|
||||
rx_synchronizer=self.rx_synchronizer,
|
||||
|
|
Loading…
Reference in New Issue